BUFFER REGISTER VHDL Search Results

16550-compatible

Abstract: uart verilog code baud rate generator vhdl sram modem AT16550-VCM1016
Contextual Info: Features • • • • • • • • Modular Design Provides Flexibility Fully Synchronous Design Testbench Included Expandable Receive and Transmit Buffers Feature and Register Compatible with 16550 UART Dual Port SRAM or Edge-triggered Register Array Used for Buffer Functions

vhdl code for rs232 receiver

Abstract: xilinx uart verilog code interface of rs232 to UART in VHDL vhdl code for uart communication vhdl code for serial transmitter vhdl code 16 bit microprocessor uart verilog code verilog code for serial transmitter verilog code for 8 bit shift register parallel to serial conversion vhdl
Contextual Info: Application Note: CPLD R UARTs in Xilinx CPLDs XAPP341 v1.3 October 1, 2002 Summary This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144, XCR3128XL, or XC2C128 CPLDs. The

block diagram 8259A

Abstract: 8259A intel 8259A 8086 interrupts application 8088 microprocessor INTEL 82C59A C8259A block diagram of Hardware and Software Interrupts of 8086 and 8088 DSA0060839.txt XC2S50-6
Contextual Info: C8259A Programmable Interrupt Controller December 6, 2001 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Core documentation Design File Formats .ngo, EDIF Netlist, VHDL Source RTL available extra Constraints File

C685

Abstract: C6850 MC6850
Contextual Info: C6850 Asynchronous Communication Interface Adapter June 26, 2000 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Core design document Design File Formats EDIF, .ngo, .XNF Netlist; VHDL Source RTL available extra

z80 microprocessor

Abstract: CZ80PIO z80-pio z80 microprocessor family CZ80CPU zilog z80 microprocessor applications z80 vhdl Z80CPU Z80PIO z80PIO vhdl
Contextual Info: CZ80PIO Peripheral device September 2001 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Core Specifications, test set details Design File Formats EDIF netlist , VHDL or Verilog Source RTL available at extra cost

mpeg 4 encoder

Abstract: video encoder mpeg DS511 interface of camera with virtex 5 fpga for image mpeg4 vhdl code for spartan 6 audio
Contextual Info: MPEG-4 Simple Profile Encoder v1.1 DS511 v1.7.1 December 15, 2006 Product Specification Introduction The Xilinx MPEG-4 Part 2 Simple Profile Encoder (MPEG-4 Encoder) core is a fully functional VHDL design implemented on a Xilinx FPGA. The MPEG-4 Encoder core accepts uncompressed video and generates compressed bit streams based on the “Information

vhdl code for a updown counter using structural m

Abstract: vhdl code for 4 bit updown counter vhdl code for a updown counter vhdl code of 4 bit comparator 4 bit updown counter vhdl code CY7C335 5bit updown counter 26CV12 26V12 PALCE22V10
Contextual Info: Designing with the CY7C335 and Warp2 VHDL Compiler This application note provides an overview of the CY7C335 Universal Synchronous EPLD architecture and Warp2® VHDL Compiler for PLDs. Example designs demonstrate how the Warp2 VHDL compiler takes advantage of the rich architectural features of the CY7C335.

vhdl code for a updown counter

Abstract: programmer manual EPLD cypress vhdl code for 4 bit updown counter 4 bit updown counter vhdl code vhdl coding CY7C335 vhdl code 26CV12 26V12 IEEE1076
Contextual Info: fax id: 6412 Designing with the CY7C335 and Warp2 Designing with the CY7C335 and Warp2 VHDL Compiler This application note provides an overview of the CY7C335 Universal Synchronous EPLD architecture and Warp2® VHDL Compiler for PLDs. Example designs demonstrate how

100-PIN

Abstract: 84-PIN PF100 PF144 PL84 QL2003 QL2003-1PF100C QL2003-1PF144C
Contextual Info: QL2003  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

40MHZ

Abstract: CY7C371 FLASH370 IEEE1164 MACH210A
Contextual Info: Getting Started Converting .ABL Files to VHDL Introduction This application note is intended to assist Warp users in converting designs written in DATA I/O’s ABEL™7 hardware description language to IEEE 1076 VHDL. It contains several language cross reference tables and many helpful hints. It

vhdl code for powerpc

Abstract: EP100 MPC8260 XCV400E-FG676
Contextual Info: EP100 PowerPC Bus Slave April 15, 2003 Product Specification AllianceCORE Facts Core Specifics See Table 1. Provided with Core Eureka Technology, Inc. Documentation User guide Design File Formats EDIF netlist Constraints File Top201.ucf Verification VHDL or Verilog test bench

fireberd

Abstract: design of HDLC controller using vhdl TTC fireberd 6000A
Contextual Info: MC-XIL-HDLC Single-Channel HDLC Controller April 15, 2003 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation User Guide, Data Sheet Design File Formats VHDL, Verilog source RTL1 Constraints File .ucf Verification

QL2005

Abstract: QL2005-1PF144C QL2005-1PQ208C 84-PIN PL84 PQ208
Contextual Info: QL2005  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

84-PIN

Abstract: PF144 PL84 PQ208 QL2007 QL2007-1PF144C QL2007-1PQ208C 208-Pin PQFP
Contextual Info: QL2007  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

Parallel-IN Serial-OUT spi

Abstract: SIPO 32bit MSB6 XC2V250-5 XC2S50-6
Contextual Info: SPI-Slave: Serial Protocol Interface-Slave February 12, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Core documentation EDIF Netlist; VHDL Source RTL Design File Formats available at extra cost

100TQFP

Abstract: 344RAM QL3040
Contextual Info: QL2003  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

8 bit microprocessor using vhdl

Abstract: vhdl code scrambler VHDL CODE FOR HDLC controller PLX9080 RFC1619 RFC1662
Contextual Info: PPP8 HDLC Core CC318f February 14, 2000 Product Specification AllianceCORE Facts C ooreEl Core Specifics See Table 1 Provided with Core Documentation Product Brief Datasheet Design Document Test Bench Design Document Test Scripts Design file formats VHDL Compiled, EDIF netlist

84-PIN

Abstract: 84-PLCC
Contextual Info: QL2005  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

208CQFP

Contextual Info: QL2007  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

Contextual Info: QL2009  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

PF144

Abstract: PQ208 QL2009 QL2009-1PB256C QL2009-1PF144C QL2009-1PQ208C
Contextual Info: QL2009  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

COMP R

Contextual Info: OPB Universal Serial Bus 2.0 Device v1.00a DS591 May 10, 2007 Product Specification Introduction LogiCORE Facts The Xilinx Universal Serial Bus 2.0 High Speed Device with On-chip Peripheral Bus (OPB) enables USB connectivity to the user’s design with a minimal amount

UT4090

Abstract: QuickLogic Military FPGA Introduction
Contextual Info: Standard Products UT4090 RadHard FPGA Advanced Data Sheet August 3, 2001, Rev D q Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation q QuickLogic existing IP such as microcontrollers, DRAM controllers, USART and PCI can be accessed

Contextual Info: QL2007 7,000 Gate pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C PRELIMINARY DATA pASIC 2 HIGHLIGHTS -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis