BS6450 Search Results

CON12

Abstract: kx-7 26 SO-64 CS61582 CS61582-IQ5 CS61584 12.352 cts
Contextual Info: CS61582 A Cirrus Logic Company D ual T1/E1 Line Interface Features General Description • The CS61582 is a dual line interface optimized for highly-integrated T1/E1 asynchronous or synchronous multiplexer applications such as SONET and SDH. Each channel features individual control and status

IR DATABOOK SCR

Abstract: cmos logic databook BTS 8800 COMCLOK 13.56 CON12 line output transformer for television Transformer te-e TTL databook TTL databook application CS61584A
Contextual Info: CS61584A Product Databook =CIRRUS LOGIC FEATURES • Dual T1/E1 Line Interface ■ 3.3 Volt and 5 Volt Versions D ual T1/E1 Line In terface ■ Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications ■ Matched Impedance Transmit Drivers

Contextual Info: CS61582 A Cirrus Logic Company Dual T1/E1 Line Interface Features General Description CS61582 is a dual line interface optimized for Dual T1/E1 Line Interface Optimized for The highly-integrated T1/E1 asynchronous or synchronous Mutiplexer Applications multiplexer applications such as SONET and SDH.

RI00P

Contextual Info: CS61582 ACfrrus Logic Company Dual T1/E1 Line Interface Features General Description • Dual T1/E1 Line Interface Optimized for Mutiplexer Applications The CS61582 is a dual line interface optimized for highly-integrated T1/E1 asynchronous or synchronous

S5025

Abstract: Ez102 T9075
Contextual Info: MT9075B M IT SL E1 Single Chip Transceiver S E M IC O N D U C T O R Prelim inary Inform ation D S5025 Features C om bined PCM 30 fram er, Line Interface Unit LIU and link co ntrollers in a 6 8 pin PLCC or 100 pin M QFP package ISSUE 2 O ctober 1998 O rdering Inform ation

DS5024

Abstract: fuses two way car alarm MO-112 MT9074 MT9074AL MT9074AP PCM30 PUB43801 SLC96
Contextual Info: MT9074 T1/E1/J1 Single Chip Transceiver Advance Information Features • • • • • • • Description The MT9074 is a single chip device, operable in either T1 or E1 mode, integrating either an advanced T1 T1 mode or PCM 30 (E1 mode) framer with a

CON12

Abstract: m-tron CS61582 CS61582-IQ5 CS61584 remote control receiver ir tv schematic
Contextual Info: CS61582 Dual T1/E1 Line Interface Features • • • • • • • General Description CS61582 is a dual line interface optimized for Dual T1/E1 Line Interface Optimized for The highly-integrated T1/E1 asynchronous or synchronous Mutiplexer Applications

so do chan 4164

Abstract: MT9075AP PE-65351 MO-112 MT9075A MT9075AL PCM30 PE-64934 Midcom PE-65
Contextual Info: MT9075A E1 Single Chip Transceiver Preliminary Information Features • • The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU interfaces the framer functions to the PCM

1n5339

Abstract: TRANSMIT CUSTOM DIODE MT9074 MT9074AL MT9074AP MT9074APR PCM30 MT9074AL1 EC90
Contextual Info: MT9074 T1/E1/J1 Single Chip Transceiver Data Sheet Features • August 2005 Combined E1 PCM30 and T1 (D4/ESF) framer, Line Interface Unit (LIU) and link controller with optional digital framer only mode • In T1 mode the LIU can recover signals attenuated by up to 30 dB (5000 ft. of 24 AWG

Contextual Info: MT9075B E1 Single Chip Transceiver Preliminary Information Features • • The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit LIU . The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with

Contextual Info: CS61584A CS61584A Dual Dual T1/E1 T1/E1 Line Line Interface Interface Features – AT&T Publication 62411 – ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l Dual T1/E1 Line Interface Volt and 5 Volt Versions l Crystal-less Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011

Contextual Info: MITEL MT9075 E1 Single Chip Transceiver Preliminary Information Features • ISSUE 2 C om bined PCM 30 fram er, Line Interface Unit LIU and link controllers in a 68 pin PLCC or 100 pin MQFP package • S electable bit rate data link access with optional S a bits HDLC con tro ller (HDLCO) and

ng52

Contextual Info: MT9075B M IT SL E1 Single Chip Transceiver S E M IC O N D U C T O R P relim inary Inform ation Features ISSUE 1 Combined PCM 30 framer, Line Interface Unit LIU and link controllers in a 6 8 pin PLCC or 100 pin MQFP package Selectable bit rate data link access with

MO-112

Abstract: MT9074 MT9074AL MT9074AP PCM30 PUB43801 SLC96 TR-62411 adi please confirm the manufacturing date from the serial number recorded on the product PSUEDO RANDOM SEQUENCE GENERATOR
Contextual Info: MT9074 T1/E1/J1 Single Chip Transceiver Data Sheet Features • • • • • • • Description The MT9074 is a single chip device, operable in either T1 or E1 mode, integrating either an advanced T1 T1 mode or PCM30 (E1 mode) framer with a Line Interface Unit (LIU).

Contextual Info: MT9074 T1/E1/J1 Single Chip Transceiver Data Sheet Features • • • • • • • Description The MT9074 is a single chip device, operable in either T1 or E1 mode, integrating either an advanced T1 T1 mode or PCM30 (E1 mode) framer with a Line Interface Unit (LIU).

g796

Abstract: DIAGRAM IC an 7582 MT9075 MT9075AP MO-112 MT9075AL PCM30 pcm ami
Contextual Info: MT9075  E1 Single Chip Transceiver Advance Information Features Combined PCM 30 framer, Line Interface Unit LIU and link controller in a 68 pin PLCC or 100 pin MQFP package Selectable rate data link access with optional Sa bits HDLC controller (HDLC0) and channel

HDB3 and CMI which is better

Abstract: M-tron CON12 SO-64 TMSLF CS61583 CS61583-IL5 CS61583-IQ5 CS61584 AMI Semiconductor remote controller
Contextual Info: CS61583 A Cirrus Logic Company D ual T1/E1 Line Interface Features General D e scrip tio n • Dual T1/E1 Line Interface The CS61583 is a dual line interface for T1/E1 applica­ tions, designed for high-volume cards where low power and high density are required. Each channel features

T-00499

Abstract: CS61318 CS61318-IL CS61318-IP LXT318 T-1068
Contextual Info: CS61318 E 1 Line Interface Unit Features Description • E1 Line Interface Unit The CS61318 is an E1 primary rate line interface unit. This device combines the complete analog transmit and receive circuitry for a single, full-duplex interface E1 rates. The device provides jitter attenuation compliant to

G732 DECODER

Abstract: TDA 1054 M Valor CS61581 CS61581-IL CS61581-IP LXT310 LXT318 Scans-0013469
Contextual Info: CS61581 P ro d u c t D a ta S h e e t = C IR R U S LOGIC FEATURES • Provides T1 and E1, Long Haul and Short Haul Line Interface ■ Provides a QRSS Test Signal and Error Detector T1/E1 U niversal Line interface ■ Impedance Matching Line Driver Using a Single

TD38-1505A

Abstract: rneg2
Contextual Info: P R E L IM IN A R Y 8/ 11/97 A Cirrus Logic Company C S 6 1 5 8 4 A Dual T1/E1 Line Interface Features General Description • Dual T1/E1 Line Interface The CS61584A is a dual line interface for T1/E1 appli­ cations, designed for high-voiume cards where low

CON12

Abstract: CS61584A CS61584A-IL3 CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ5 BIPOLAR MEMORY
Contextual Info: CS61584A Dual T1/E1 Line Interface Features – AT&T Publication 62411 – ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l Dual T1/E1 Line Interface Volt and 5 Volt Versions l Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications

ASD 800 ASD 810

Abstract: LS 1017 TRANSFORMER BTS 8800 CON12 CS61584A CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ5 BIPOLAR MEMORY RV-1 1k
Contextual Info: CS61584A CS61584A Dual Dual T1/E1 T1/E1 Line Line Interface Interface Features – AT&T Publication 62411 – ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l Dual T1/E1 Line Interface Volt and 5 Volt Versions l Crystal-less Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011

DS5024

Abstract: EC901 MAKING CODE 1H sod
Contextual Info: 0 MITEL MT9074 T1/E1/J1 Single Chip Transceiver Advance Information S E M IC O N D U C T O R Features • • • • DS5024 Combined E1 PCM 30 and T1 (D4/ESF) framer, Line Interface Unit (LIU) and link controller with optional digital framer only mode In T1 mode the LIU can recover signals attenuated

r2561

Abstract: COMCLOK 13.56 CON12 m-tron M-tron 1 mhz crystal oscillator CS61583 CS61583-IL5 CS61583-IQ5 CS61584 1X326
Contextual Info: CS61583 Dual T1/E1 Line Interface Features General Description • • The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. Each channel features individual control and status pins which eliminates the