BLM31B601S Search Results

AMCC S2060

Abstract: RX-6 TX-6 h d 2001 BLM31B601S S2060 S2060A S2060B S2060C S2060D VJ0612
Contextual Info: DEVICE SPECIFICATION GIGABIT ETHERNET TRANSCEIVER GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION FEATURES • • • • • • • • • • • • • Operating rate 1250 MHz Gigabit Ethernet line rates Half and full VCO output rates Functionally compliant IEEE 802.3z Gigabit

BLM31b601s

Abstract: BLM11B601SPB OC-24 S3076 BLM11B601S
Contextual Info: Part Number S3076 Revision 1.1 - May 18, 2000 S3076 PRELIMINARY APPLICATION NOTE Board Decoupling Guidelines MULTI-RATE SONET/SDH/CLOCK RECOVERY UNIT The S3076 supports clock recovery for the OC-48, OC-24, Gigabit Ethernet, OC-12, or OC-3 data rates. The CAP1/CAP2 capacitor should be 10 µF in series with 56 Ω resistors. Figure 1 illustrates the connections for the

7476 counter

Abstract: pin diagram of ttl 7476 7476 PIN DIAGRAM pin diagram of 7476 ttl 7476 datasheets EMR1 7476 ttl datasheets LM393D-SO8 APPLICATION NOTES 7476 st9 technical manual
Contextual Info: ST92F150-EMU2 HDS2V2 Emulator User Manual Release 1.1 July 2001 Ref: DOC-ST92F150-EMU2 INSTRUCTIONS FOR USE—WARNING This product is conform to the 89/336/EEC Directive. It complies with the ITE EN55022 standard for EMC emissions and generic 50082-1 1992 edition immunity standards.

BLM11B601S

Abstract: blm11b601 BLM11B601SPB BLM31b601s BLM31B601SPB S3033
Contextual Info: Part Number S3033 Revision 1.0 - March 14, 2001 S3033 APPLICATION NOTE Board Decoupling Guidelines SONET/SDH/ATM OC-3/12 Transceiver S3033 Example The S3033 transceiver chip is a fully integrated serialization/deserialization SONET OC-12 622.08 Mbit/s and

Contextual Info: >4 M C C PRELIMINARY DEVICE SPECIFICATION • Switched networks • Data broadcast environments FEATURES • Repeater with parallel monitor function • Proprietary extended backplanes • Selectable parallel input provides local control of serial bit stream

n55t

Contextual Info: DEVICE SPECIFICATION FEATURES • 1062 MHz Fibre Channel line rates • Half and full VCO output rates • Functionally compliant ANSI X3T11 Fibre Channel Specification • Transmitter incorporating phase-locked loop (PLL) clock synthesis from low speed reference

BLM31B601S

Abstract: S2062 S2067 VJ0612
Contextual Info: Part Number S2067 Revision 1.0 - February 28, 2000 S2067 APPLICATION NOTE Application Note and Reference Diagrams Introduction This document is intended to assist customers in using AMCC's S2067 dual channel physical layer device. Details concerning application information, circuit design, layout, and component selection are provided to help insure firstpass success in implementing a functional design with optimal signal quality. This document should be used in conjunction with the product device specification. An elementary knowledge of high-speed printed circuit layout

BLM31B601SPB

Abstract: BLM31b601s S3024
Contextual Info: DECOUPLING APPLICATION NOTE DECOUPLING APPLICATION NOTE S3024 S3024 SONET/SDT/ATM S3024 Example The S3024 Clock Recovery Unit CRU contains a stand-alone CRU PLL. The CAP1/CAP2 pins should be connected to a 1.0 µF capacitor in series with 82Ω resistors. Figure 1 illustrates the connections for the S3024

BLM31B601S

Abstract: S2062 VJ0612 UFC100 S2078
Contextual Info: Part Number S2078 Revision 1.0 - February 25, 2000 S2078 APPLICATION NOTE Application Note and Reference Diagrams Introduction This document is intended to assist customers in using AMCC's S2078 dual channel physical layer device. Details concerning application information, circuit design, layout, and component selection are provided to help insure firstpass success in implementing a functional design with optimal signal quality. This document should be used in conjunction with the product device specification. An elementary knowledge of high-speed printed circuit layout

BLM31B601S

Abstract: S2076 VJ0612 2S2076
Contextual Info: Part Number S2076 Revision 1.0 - March 24, 2000 S2076 APPLICATION NOTE Application Note and Reference Diagrams Introduction This document is intended to assist customers in using AMCC's S2076 quad channel physical layer device. Details concerning application information, circuit design, layout, and component selection are provided to help insure first-pass success in implementing a functional design with optimal signal quality. This document should be

BLM31B601SPB

Abstract: S3026 S3026A S3026A-1
Contextual Info: DECOUPLING APPLICATION NOTE DECOUPLING APPLICATION NOTE S3026 S3026 SONET/SDT/ATM S3026 Example The S3026 Clock Recovery Unit CRU contains a stand-alone CRU PLL. The CAP1/CAP2 pins should be connected to a 1.0 µF in series with two resistors (see Table 1). Figure 1 illustrates the connections for the

E23 SMD Transistor

Abstract: SMD e23 smd transistor E23 TLV5540 BLM31B601SPT smd transistor E33 tlc5560 E30 E30 E33 SOT-23 TLC5510 74AC11004B
Contextual Info: TLC5540/TLC5510/TLC5510A/ TLV5540/TLV5510 Evaluation Module User’s Guide 1999 Mixed-Signal Products SLAU007C IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

BLM31b601s

Abstract: VJ0612
Contextual Info: Part Number S2072 Revision 1.0 - August 14, 2000 S2072 DECOUPLING APPLICATION NOTE FOUR PORT BYPASS AND REPEATER FOR FC-AL S2072 Decoupling Layout The S2072 Four Port Bypass and Repeater contains a Clock and Data Recovery CDR PLL. The LPF1/LPF2 pins should be connected to a 2.2 µF (X7R Type) capacitor in series with 24 Ω resistors. Figure 1 illustrates the power

BLM11B601S

Abstract: BLM11B601SPB BLM31B601SPB S3033
Contextual Info: Part Number S3033 Revision 1.0 - January 20, 2000 S3033 APPLICATION NOTE Board Decoupling Guidelines SONET/SDH/ATM OC-3/12 Transceiver S3033 Example The S3033 transceiver chip is a fully integrated serialization/deserialization SONET OC-12 622.08 Mbit/s and

SG-45 diode

Abstract: NFA62R10C223 sg 421 varistor 168t3 NFM46P11C155 DSS306-55 F223Z16 BL01RN1-A62B1 nfa 102 murata IC 7404 NFA41R10C223
Contextual Info: This is the PDF file of catalog No.C31E-4. No.C31E4.pdf 99.8.20 On-Board Type DC EMI Suppression Filter (EMIFIL ) EMI SUPPRESSION FILTER Murata Manufacturing Co., Ltd. Cat.No.C31E-4 This is the PDF file of catalog No.C31E-4. No.C31E4.pdf 99.8.20 MURATA entered the suppression filter field at an early

D223S

Abstract: D223S12-22 NFM2012P13C104R 9946DC b050s DSS306FZ103N100 nfa 102 murata NFM46P11C155 DSS306-FZ103N100 NFM60R30T222
Contextual Info: このカタログはNo.C31-6をムラタのwebサイトよりPDF形式でダウンロードしたものです。 C31J6.pdf 99.4.6 オンボードタイプ（DC用） EMI除去フィルタ（エミフィル ） EMI SUPPRESSION FILTER Cat.No.C31-6 このカタログはNo.C31-6をムラタのwebサイトよりPDF形式でダウンロードしたものです。

BLM31B601S

Abstract: EV3038 S3038 SJ300 VJ0612 FERRITE E15 SJ-300
Contextual Info: SONET/SDH/ATM OC-12 QUAD TRANSCEIVER EVALUATION BOARD SONET/SDH/ATM OC-12 QUAD TRANSCEIVER EVALUATION BOARD EV3038 EV3038 DESCRIPTION The S3038 evaluation board provides a flexible platform for verifying the operation of the S3038 Quad Transceiver interface circuit. This document provides information on the board contents. It should be used in conjunction with the S3038 data sheet, which contains full technical details on the chips operation.

S2060A

Abstract: S2060 BLM31B601S S2060B S2060C S2060D VJ0612 23-CORE
Contextual Info: DEVICE SPECIFICATION GIGABIT ETHERNET TRANSCEIVER GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION FEATURES • • • • • • • • • • • • • Operating rate 1250 MHz Gigabit Ethernet line rates Half and full VCO output rates Functionally compliant IEEE 802.3z Gigabit

pt 4115 EQUIVALENT

Contextual Info: PRELIMINARY DEVICE SPECIFICATION C G IG A B IT ETH ER N ET TR AN SC EIVER FEATURES • • • • • • • • • • • • • Operating rate 1250 MHz Gigabit Ethernet line rates Half and full VCO output rates Functionally compliant IEEE 802.3z Gigabit

SIEMENS capacitor tantalum

Abstract: siemens matsua ceramic filter 63d40
Contextual Info: TitlePage - 80A1010_MA001_05 PowerSpan II PowerPC-to-PCI Bus Switch User Manual Document Number: 80A1010_MA001_05 Document Status: Final Release Date: November 2002 This document discusses the features, capabilities, and configuration requirements of the PowerSpan II. It is intended for

t428 motorola

Abstract: compaq 325 63d40 Motorola XHW
Contextual Info: TitlePage - 80A1010_MA001_07 PowerSpan II PowerPC-to-PCI Bus Switch User Manual Document Number: 80A1010_MA001_07 Document Status: Final Release Date: April 2003 This document discusses the features, capabilities, and configuration requirements of the PowerSpan II. It is intended for

IC 7404

Abstract: BL01RN1A62T5 nfa 102 murata NFM46P11C155 sg 421 varistor Inductive current sensor of measurement PLT09H INDUCTOR CHIP FERRITE BEAD 3216 murata BNX 3 terminal capacitor
Contextual Info: This is the PDF file of catalog No.C31E-3. No.C31E3.pdf 98.9.29 On-Board Type DC EMI Suppression Filter (EMIFIL ) EMI SUPPRESSION FILTER Murata Manufacturing Co., Ltd. Cat.No.C31E-3 This is the PDF file of catalog No.C31E-3. No.C31E3.pdf 98.9.29 MURATA entered the suppression filter field at an early

BLM31B601S

Abstract: S2070 S2070A S2070B VJ0612
Contextual Info: DEVICE SPECIFICATION FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION FEATURES • • • • • • • • • • • • • 1062 Mbps Fibre Channel line rates 1250 Mbps (Gigabit Ethernet) line rates

S3050

Abstract: BLM11B601S BLM31B601SPB BLM11B601SPB OC-24
Contextual Info: PLL BOARD DECOUPLING GUIDELINES BOARD DECOUPLING GUIDELINES S3050 S3050 MULTI-RATE SONET/SDH/CLOCK RECOVERY UNIT The S3050 supports clock recovery for the OC-48, OC-24, Gigabit Ethernet, OC-12, or OC-3 data rates. The CAP1/CAP2 capacitor should be 22 µF with series 24Ω resistors and 150kΩ resistors to VCC. The figure below