BINARY COUNTER CD 93 Search Results

RCA-CD4518

Abstract: 3FT 87 and/icl+7060
Contextual Info: CD451ÖB, CD4520B Types 4 SI 8 B CMOS Dual Up-Counters High-Voltage Types 20-Volt Rating Features: CD4518B Dual B CD Up-Counter CD4520B Dual Binary Up-Counter • Medium-spaed operation 6-MHz typical dock frequency at 10 V ■ Positive- or negative^dge triggering

Contextual Info: M MOTOROLA. SN54/74LS90 SN54/74LS92 SN54/74LS93 DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER The SN 54/74LS 90, S N 54/74LS 92 and S N 54/74LS 93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or

74HC4052E

Abstract: 74HC194E 74HC4046AE 74HC4067E 74HC4538E 74HCT4511E 54HCT20 74HC4060E 074h 74hct27e
Contextual Info: Product Selectors Index to Devices CMOS Logic TTL Logic Plastic Pkg. CERDIP Plastic Pkg. C D 74H C 00E .M CD 74H C 02E.M C D 74H C 03E .M •C D 7 4H C 04 E .M C D 74H C 08E.M CD 54H C 00F CD 54H C 02F CD 54H C 03F •C D 5 4 H C 0 4 F CD 54H C 08F C D 74H CT00E.M

circuit diagram of full subtractor circuit

Abstract: 266 XnOR GATE full subtractor circuit using nor gates CBD41 LD74 0-99 counter by using 4 dual jk flip flop xnor ne 5555 timer gray code 2-bit down counter LD78
Contextual Info: ispLSI Macro Library Reference Manual Version 8.0 Technical Support Line: 1-800-LATTICE or 408 428-6414 DSNEXP-ISPML-RM 8.0.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

8 bit full adder

Abstract: LD78 CDUD4 CBU12 266 XnOR GATE BI48 CBD12 FD51 mux24 MUX82
Contextual Info: ispLSI Macro Library Reference Manual Version 8.2 Technical Support Line: 1-800-LATTICE or 408 826-6002 IDE-ISPML-RM 8.2.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

4-bit even parity checker

Abstract: right left shift register 12 bit binary multiplier 5 bit binary multiplier VSC160 8bit to bcd priority encoder 8 bit multiplier with shift register 5 bit binary parallel multiplier synchronous binary counter with latch VSC191
Contextual Info: T T L MACRO LIBRARY CELL NAME V SC85 V SC90 V SC92 V SC93 VSC94 V SC95 VSC137 VSC138 VSC148 VSC150 VSC154 VSC157 VSC160 VSC161 VSC162 VSC163 VSC164 VSC165 VSC166 VSC168 VSC169 VSC173 VSC174 VSC175 VSC160 VSC181 VSC182 VSC190 DESCRIPTION G ATE COUNT 4-Bit Magnitude Comparator

SN74AS897

Abstract: ctr16 ih21 ik91 IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER SN54AS897A ZN410
Contextual Info: SN54AS897A, SN74AS897A 16•BIT PARALLEL/SERIAL BARREL SHIFTERS D2885. OCTOBER 1985-REVISED MARCH 1986 SN54AS897A.SN74AS897A G8 PIN-GRID ARRAY PACKAGE • High-Speed "Flash" Shift Operations • Expandable to 32 Bits • Hexadecimal and' Binary Normalization with

Contextual Info: g MC54/74HC93 M OTOROLA Product P r e v ie w HIGH-PERFORMANCE CMOS LOW -POWER CO M PLEM EN TAR Y MOS SILICON-GATE 4-STAGE BINARY RIPPLE COUNTER WITH - 2 AND ^ 8 SECTIONS 4-STAGE BINARY RIPPLE COUNTER WITH - 2 AND - 8 SECTIONS The M C 54/74H C 93 is identical in p in o u t to the LS93. The device in­

HEF4029BP

Abstract: 7Z69575 HEF4029B HEF4029BD HEF4029BT HEF4071B HIGH FREQUENCY DECADE COUNTER
Contextual Info: HEF4029B MSI J V . SYNCHRONOUS UP/DOWN COUNTER, BINARY/DECADE COUNTER The HEF4029B is a synchronous edge-triggered up/down 4-b it binary/BCD decade counter w ith a clock in pu t CP , an active LOW count enable input (CE), an up/down control in pu t (UP/DN), a

Contextual Info: S G S-THOMSON 7^2^237 42E » G 03 331 2 4 BISGTHt T74LS90 T74LS92/93 r r r sGS-THomsGPi COUNTERS: LS90 DECADE LS92 DIVIDE BY TWELVE LS93 4-BIT BINARY ~ T 'V 5 '2 3 - / 3 a LOW POWER CONSUMPTION TYPICALLY 45 mW • HIGH COUNT RATES TYP 50 MHz . CHOICE OF COUNTING MODES BCD, BI-QUINARY, DIVIDE-BY-TWELVE BINARY

T74LS90

Abstract: modulo-12 T74LSXX
Contextual Info: SGS-THOMSON IQÂÏÏMSOtgS T74LS90 T74LS92/93 COUNTERS: LS90 DECADE LS92 DIVIDE BY TWELVE LS93 4-BIT BINARY • LOW POWER CONSUMPTION TYPICALLY 45 mW ■ HIGH COUNT RATES TYP 50 MHz ■ CHOICE OF COUNTING MODES BCD, BI-QUINARY. DIVIDE-BY-TWELVE BINARY ■ INPUT CLAMP DIODES LIMIT HIGH SPEED

HEF4024B

Abstract: f 4024b binary counter CD 93
Contextual Info: HEF4024B , ^ _MSI 7-STAGE BINARY COUNTER The HEF4024B is a 7-stage binary ripple counter with a clock input CP , and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Oo to Og). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages end forces all outputs

IL44

Abstract: ASYNCHRONOUS COUNTER UP FUNCTION OF PRESET 1-BIT D Latch IL44 J FD14E 2 SD 106 AI OL41s 8 shift register by using D flip-flop ID31E OD34E
Contextual Info: ispLSI 5K/8K Macro Library Supplement Version 8.0 Technical Support Line: 1- 800-LATTICE or 408 428-6414 DSNEXP-ISPMLS Rev 8.01 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

930 series dtl

Abstract: 830 dtl DTL 957 dtl 948 expandable dual 4 input NAND DTL 950 motorola flip-flop 948 A9611 DTL 937
Contextual Info: LANSDALE SEMICONDUCTOR 32E D • 5 3 b S fl0 3 □□□□355 5 HLTE T -43-01 MAXIMUM RATINGS Rating Supply Operating Voltage Range - Vcc DTL MOTOROLA INTEGRATED CIRCUITS 930 Series 830 Series These MDTL integrated circuits provide an excellent balance of

54C90

Contextual Info: Semiconductor February 1988 MM54C90/MM74C90 4-Bit Decade Counter MM54C93/MM74C93 4-Bit Binary Counter General Description The MM54C90/MM74C90 decade counter and the MM54C93/MM74C93 binary counter and complementary MOS CMOS integrated circuits constructed with N- and

SN72710L

Abstract: MC1013P MC680P 796HC mc1235l MC838P MC814G MC1670L 723HC 741hm
Contextual Info: 27-18 LH 0002 C LH 0002 CN 586-81! .587-270 AMPEX CURRENT A M PLIFIE R IN PUT 27-18 AMPEX REV 111 NH 0005C 586-495 D AC08CZ 587-896 27 + R ef | 1_ O PE R ATIO N AL A M PLIFIE R 8 BIT D -A CONVERTER 2" 14 13 12 11 6 5 4 1I i i i i i 3 1 13 , +12V So-4

Contextual Info: February 1992 Semiconductor DM74LS197 Presettable Binary Counters General Description The ’LS197 ripple counter contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter. State changes are initiated by the falling edge of the clock. The ’LS197 has a Master Re­

EL-7L

Abstract: Q1147 Modulo 7 counter ScansUX985
Contextual Info: TTLVNISI 9305 VARIABLE MODULO COUNTER DESCRIPTION — The T T L /M S I 9305 is a m o n o lith ic, high speed, Variable M odulo Counter circu it, constructed w ith the Fairchild Planar* epitaxial process. It is a semisynchronous counter w hich can be programmed w ith o u t extra logic to provide division o r counting by either 2 and 4, 5, 6 , 7, 8 , or

HBF4727A

Abstract: ZD 607 - triac ZD 607 - triac circuit hbf 4727a TDA3310 hbf4727 HBF4740 DTL-930 7-stage frequency divider BF479S
Contextual Info: / h o f t f o f m A T E ^SEMICONDUCTOR “ PRODUCTS 1979/80 I NT RODUCTI ON This publication aims to provide condensed information on the vast range of standard devices currently produced by SGS-ATES. For easy consultation the products have been divided into several sections according to the main product

DM7493A

Contextual Info: DM5490/DM7490A, DM7493A Decade and Binary Counters General Description Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the 90A and divideby-eight for the 93A.

Contextual Info: Objective specification Philips Semiconductors Programmable ripple counter with 74HC/HCT9323A oscillator; DESCRIPTION FEATURES T he 74H C /H C T 9323 A are high-speed Si*gate C M O S devices. They • 8-pin space saving package

hef4029bp

Abstract: HEF4029 HEF4029BPN
Contextual Info: HEF4029B MSI SYNCHRONOUS UP/DOWN COUNTER, BINARY/DECADE COUNTER The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input CP , an active LOW count enable input (CE), an up/down control input (UP/BN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

RADIO SHACK PARTS CROSS REF

Abstract: 273-060a ULN2003 PIN DIAGRAM configuration HDS-200 ULN2003 PIN DIAGRAM heart rate monitor lm324 M68HC05 ULN2003 RELAY DRIVER phase controller L120 THERMOSTAT SCHEMATIC
Contextual Info: M68HC05 Applications Guide M68HC05 Microcontrollers M68HC05AG/D Rev. 4, 3/2002 WWW.MOTOROLA.COM/SEMICONDUCTORS M68HC05 Applications Guide To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed

lm324 diagram

Abstract: RADIO SHACK PARTS CROSS REF phase controller L120 heart rate monitor lm324 273-060a motorola 68hc05 schematic programmer uln2003 THERMOSTAT SCHEMATIC xbee-p piezo air pressure sensor IC
Contextual Info: M68HC05AG/AD Rev. 3 HC 5 M68HC05 Applications Guide N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D R E Q U I R E D N O N - D I S C L O S U R E Applications Guide A G R E E M E N T M68HC05 Microcontroller Motorola, Inc., 1996; All Rights Reserved