BD 4070 TRANSISTOR Search Results

Contextual Info: C O S /M O S IN T EG R A T ED CIRCUITS p> ÀZ Ì L O T T 'S „ Eh cf S b HCC/HCF 4077B 4070B - QUAD EXCLUSIVE-O R GATE 4077B - QUAD EXCLUSIVE-NO R GATE • • • • • • MEDIUM-SPEED OPERATION tpHL= tp LH= 70 ns TYP. AT V cc = 10V, CL= 50 pF QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE

thermistor ntc 10k

Abstract: NTC 5,0
Contextual Info: LTC4070 Li-Ion/Polymer Shunt Battery Charger System FEATURES n n n n n n n n n DESCRIPTION Low Operating Current 450nA 1% Float Voltage Accuracy Over Full Temperature and Shunt Current Range 50mA Maximum Internal Shunt Current (500mA with External PFET)

solar charger schematic 24V

Abstract: solar charger schematic 12V g14 NTC NTC 1K 4070 CMOS Bd 4070 transistor 4070 data sheet solar charger schematic diagram solar shunt regulator fdn352ap
Contextual Info: LTC4070 Li-Ion/Polymer Shunt Battery Charger System FEATURES DESCRIPTION n The LTC 4070 allows simple charging of Li-Ion/Polymer batteries from very low current, intermittent or continuous charging sources. The 450nA to 50mA operating current makes charging possible from previously unusable

thermistor ntc 10k

Contextual Info: LTC4070 Li-Ion/Polymer Shunt Battery Charger System FEATURES DESCRIPTION n The LTC 4070 allows simple charging of Li-Ion/Polymer batteries from very low current, intermittent or continuous charging sources. The 450nA to 50mA operating current makes charging possible from previously unusable

C 3355 transistor

Contextual Info: MC10E122, MC100E122 5V ECL 9-Bit Buffer The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

C 3355 transistor

Contextual Info: MC10E131, MC100E131 5V ECL 4-Bit D Flip-Flop The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock CC LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE

marking CODE D2B

Contextual Info: MC10E457, MC100E457 5V ECL Triple Differential 2:1 Multiplexer The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The fully differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The higher frequency outputs provide the device with a > 1.0 GHz

MC10E142FN

Abstract: MC10E142FNR2 E142 MC100E142 MC100E142FN MC100E142FNR2 MC10E142
Contextual Info: MC10E142, MC100E142 5VĄECL 9ĆBit Shift Register The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 – D8 accept parallel input data, while S-IN accepts serial input

MC100E175

Abstract: E175 MC100E175FN MC100E175FNR2 MC10E175 MC10E175FN MC10E175FNR2 E175 transistor
Contextual Info: MC10E175, MC100E175 5VĄECL 9ĆBit Latch With Parity The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs ODDPAR is HIGH if an odd number of the inputs are HIGH . The E175 can also be used to generate byte parity by using D8 as the

E112

Abstract: E212 MC100E212 MC100E212FN MC100E212FNR2 MC10E212 MC10E212FN MC10E212FNR2
Contextual Info: MC10E212, MC100E212 5V ECL 3-Bit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to

MC100E171

Abstract: MC100E171FN MC100E171FNR2 MC10E171 MC10E171FN MC10E171FNR2 D1C marking
Contextual Info: MC10E171, MC100E171 5VĄECL 3ĆBit 4:1 Multiplexer The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

MC100E164

Abstract: MC100E164FN MC100E164FNR2 MC10E164 MC10E164FN MC10E164FNR2 MAX5971
Contextual Info: MC10E164, MC100E164 5VĄECL 16:1 Multiplexer The MC10E/100E164 is a 16:1 multiplexer with a differential output. The select inputs SEL0, 1, 2, 3 control which one of the sixteen data inputs (A0 – A15) is propagated to the output. Special attention to the design layout results in a typical skew

MC100E166

Abstract: MC100E166FN MC100E166FNR2 MC10E166 MC10E166FN MC10E166FNR2 0180T
Contextual Info: MC10E166, MC100E166 5VĄECL 9ĆBit Magnitude Comparator The MC10E/100E166 is a 9-bit magnitude comparator which compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other. The 100 Series contains temperature compensation.

MC100E156

Abstract: MC100E156FN MC100E156FNR2 MC10E156 MC10E156FN MC10E156FNR2 0180T
Contextual Info: MC10E156, MC100E156 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic

MC100E160

Abstract: MC100E160FN MC100E160FNR2 MC10E160 MC10E160FN MC10E160FNR2
Contextual Info: MC10E160, MC100E160 5VĄECL 12ĆBit Parity Generator/Checker The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input EN forces the Q output LOW. The 100 Series contains temperature compensation.

MC100E158

Abstract: MC100E158FN MC100E158FNR2 MC10E158 MC10E158FN MC10E158FNR2
Contextual Info: MC10E158, MC100E158 5VĄECL 5ĆBit 2:1 Multiplexer The MC10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input SEL . The 100 Series contains temperature compensation. • • • • • •

MC100E167

Abstract: MC100E167FN MC100E167FNR2 MC10E167 MC10E167FN MC10E167FNR2
Contextual Info: MC10E167, MC100E167 5VĄECL 6ĆBit 2:1 MuxĆRegister The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop

E141

Abstract: E241 MC100E141 MC100E141FN MC100E141FNR2 MC10E141 MC10E141FN MC10E141FNR2 TRANSISTOR bd 181
Contextual Info: MC10E141, MC100E141 5VĄECL 8ĆBit Shift Register The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0 – D7 accept parallel input data, while

MC100E256

Abstract: MC100E256FN MC100E256FNR2 MC10E256 MC10E256FN MC10E256FNR2
Contextual Info: MC10E256, MC100E256 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

MC100E457FN

Abstract: MC100E457FNR2 MC10E457 MC10E457FN MC10E457FNR2 MC100E457
Contextual Info: MC10E457, MC100E457 5VĄECL Triple Differential 2:1 Multiplexer The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The fully differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The higher frequency outputs provide the device with a > 1.0 GHz

Contextual Info: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.

mr 4020 pin assignment

Abstract: E137 MC100E137 MC100E137FN MC100E137FNR2 MC10E137 MC10E137FN MC10E137FNR2 LM 4800 100E137
Contextual Info: MC10E137, MC100E137 5VĄECL 8ĆBit Ripple Counter The MC10E/100E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLinPSt output edge rates. This allows the counter to operate at very high frequencies while

MC100E446

Abstract: MC100E446FN MC100E446FNR2 MC10E446 MC10E446FN MC10E446FNR2
Contextual Info: MC10E446, MC100E446 5VĄECL 4ĆBit Parallel/Serial Converter The MC10E/100E446 is an integrated 4-bit parallel to serial data converter. The device is designed to operate for NRZ data rates of up to 1.3 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for

MC100E445

Abstract: MC100E445FN MC100E445FNR2 MC10E445 MC10E445FN MC10E445FNR2 DN1 marking
Contextual Info: MC10E445, MC100E445 5VĄECL 4ĆBit Serial/Parallel Converter The MC10/100E445 is an integrated 4-bit serial to parallel data converter. The device is designed to operate for NRZ data rates of up to 2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for