BCM1250
Abstract: BCM91250E
Contextual Info: BCM91250E PCI EVALUATION BOARD FOR BCM1250 SUMMARY OF BENEFITS FEATURES • BCM1250 System-on-a-Chip SOC • One serial port on I/O bracket • Dual 64-bit MIPS processors running at current sampling speed • 32-KB instruction and 32-KB data cache • 512K L2 cache
|
Original
|
bcm91250ebcm125064-bit32-kb+4256-mb32-bit33/66-mhz10/100/1000base-t
|
PDF
|
BCM1250
Abstract: BCM91250E BCM12
Contextual Info: BCM91250E PRODUCT Brief P C I E VA L U AT I O N B O A R D F O R B C M 1 2 5 0 B C M 9 1 2 5 0 E F E AT U R E S • BCM1250 System on a Chip SOC • Dual 64-bit MIPS processors running at current sampling speed • 32-KB instruction and 32-KB data cache
|
Original
|
bcm91250ebcm125064-bit32-kb+5256-mb32-bit33/66-mhz10/100/1000base-tbcm12
|
PDF
|
BCM1250
Abstract: BCM5238 BCM5615 BCM5840 BCM91250A BCM91250E MIPS64 Broadcom HT-2100
Contextual Info: BCM1250 PRODUCT Brief BCM1250 HIGH-PERFORMANCE, INTEGRATED 64-BIT MULTIPROCESSOR B C M 1 2 5 0 F E AT U R E S • Two 64-bit MIPS CPUs, scalable from 600 MHz–1 GHz • Quad-issue in order pipeline; dual execute, dual memory pipes • Enhanced skew pipeline enables zero load-to-use penalty
|
Original
|
bcm125064-bit32-kb1250-pb06-r-3+7bcm5238bcm5615bcm5840bcm91250abcm91250emips64broadcom ht-2100
|
PDF
|
SMII SGMII Bridge
Abstract: BCM91250A BCM1250A BCM5615 BCM1250 BCM5238 BCM5840 BCM91250E MIPS64 BCM91250
Contextual Info: BCM1250 PRODUCT Brief BCM1250 HIGH-PERFORMANCE, INTEGRATED 64-BIT MULTIPROCESSOR B C M 1 2 5 0 F E AT U R E S • Two 64-bit MIPS CPUs, scalable from 600 MHz–1 GHz • Quad-issue in order pipeline; dual execute, dual memory pipes • Enhanced skew pipeline enables zero load-to-use penalty
|
Original
|
bcm125064-bit32-kb64-bix+101250-pb09-rsmii sgmii bridgebcm91250abcm1250abcm5615bcm5238bcm5840bcm91250emips64bcm91250
|
PDF
|
FET k163
Abstract: AMD 140 Socket AM3 BCM91250A 60R100M6A EPM3256ATC144-7 QTE-080 k163 BCM1125 RJ45INTLED amd am2 socket pin diagram
Contextual Info: Stratix PCI Development Board September 2003, ver. 2.0 Introduction Data Sheet This data sheet describes the features and technical details of the StratixTM PCI development board. Slightly different versions of the board are included in the following development kits:
|
Original
|
pci-board/s25pci-board/s60fet k163amd 140 socket am3+8bcm91250a60r100m6aepm3256atc144-7qte-080k163bcm1125rj45intledamd am2 socket pin diagram
|
PDF
|
BELFUSE
Abstract: BCM5241 Marvell 88e6065 88E1149 88e6046 BCM5398 88e6065 88e6035 88E6185 bcm5482
Contextual Info: Recommended Products & IC Cross Reference www.belfuse.com Bel Stewart Connector Recommended Standard MagJack Part Numbers 10/100 BaseTX Single Port MagJack® 10/100 BaseTX Single Port With LEDs Without LEDs Standard RoHS Standard RoHS Tab Up, AutoMDIX, Reflow Compatible
|
Original
|
si-50170si-50170-fsi-50177si-50177-f+16si-50196si-50196-fsi-50193si-50193-fsi-40139si-60001-fbelfusebcm5241marvell 88e606588e114988e6046bcm539888e606588e603588e6185bcm5482
|
PDF
|
BCM1250
Abstract: BCM91250A MIPS64 BCM5238 BCM5615 BCM5840 BCM91250E BCM912 50Gbps
Contextual Info: BCM1250 HIGH-PERFORMANCE, INTEGRATED 64-BIT MULTIPROCESSOR SUMMARY OF BENEFITS FEATURES • Two scalable 64-bit MIPS CPUs • 600 MHz–800 MHz • Quad-issue in order pipeline; dual execute, dual memory pipes • Enhanced skew pipeline enables zero load-to-use penalty
|
Original
|
bcm125064-bit32-kb1250-pb11-r+8bcm91250amips64bcm5238bcm5615bcm5840bcm91250ebcm91250gbps
|
PDF
|
BCM1250
Abstract: BCM5238 BCM5615 BCM5840 BCM91250A BCM91250E MIPS64
Contextual Info: BCM1250 PRODUCT Brief BCM1250 HIGH-PERFORMANCE, INTEGRATED 64-BIT MULTIPROCESSOR B C M 1 2 5 0 F E AT U R E S • Two 64-bit MIPS CPUs, scalable from 600 MHz–1 GHz • Quad-issue in order pipeline; dual execute, dual memory pipes • Enhanced skew pipeline enables zero load-to-use penalty
|
Original
|
bcm125064-bit32-kb1250-pb05-r-12+6bcm5238bcm5615bcm5840bcm91250abcm91250emips64
|
PDF
|
sgmii fpga
Contextual Info: BCM1250 HIGH-PERFORMANCE, INTEGRATED 64-BIT MULTIPROCESSOR SUMMARY OF BENEFITS FEATURES • Two scalable 64-bit MIPS CPUs • 600 MHz–1 GHz • Quad-issue in order pipeline; dual execute, dual memory pipes • Enhanced skew pipeline enables zero load-to-use penalty
|
Original
|
bcm125064-bit32-kb1250-pb10-r+1sgmii fpga
|
PDF
|