B624D Search Results

Contextual Info: RGB624/B624DB 1.0 Microprocessor Access As seen on th e m icroprocessor bus th e re are eight I/O addresses, selected by RS[2:0]. Two indirect schemes are used to access all of th e in te rn a l registers and arrays through th ese eight prim ary I/O addresses.

Contextual Info: 1 1111111111111 111111 1 1111111111111 1 1111111111111 1 1111111111111 1 1 A1234564789AABCDCEFCAFBAAA AAAAAAAA AA AAAAAAAA A AAAAAAAA A AAAAAAAA A A CA7E 3CD1AEA !F"#$%&'A A6 57 *A(BA1EEA"#$ACCDCB A5+,36-!,56+A.A 12345647891 23 1 34566 1 789 1 ABCDEF86 1 7B5E 1 ADEFD9 1 FBE 1 34566 1 589B4592B1

b624

Contextual Info: RGB624/B624DB 21.0 Change Summary _ Table 25. Summary of Changes Date Changes 02/06/95 1. 10/09/95 T h is re visio n adds th e R G B 624D B p ro d u ct; th e d o cu m e n t becomes a co m b in e d R G B 624/R G B 624D B d a ta

DF0001

Abstract: RGB624
Contextual Info: RGB624/B624DB D.O PLL Compatibility Programming REF DIV COUNT R e fe re n c e D ivide C o u n t This The RG B51x and RGB52x products all have a program­ mable P L L for generating a pixel clock, and the RG B524 and RG B528 have a second P L L for driving a "S Y S C L K "

RGB624

Abstract: C2-M3
Contextual Info: RGB624/B624DB 2.0 Clocking 2.1 Clock Generators T h ere are tw o on-board clock generators: p ixe l clock and system clock SYSC LK . Each clock g e n e ra to r uses a separate p ro gram m able phase locked loop (P LL). T h is causes th e S Y S C LK s ta rt up frequency to be

PIX-1400

Contextual Info: RGB624/B624DB 3.0 Modes of Operation Pixel data can come from the V G A port or the VRAM pixel port, as selected by the P O R T S E L bit of the M is­ cellaneous Control 2 register. If the V R A M pixel port is selected, the pixel format can be 4 B P P bits per pixel , 8 BPP, 15/16 BPP, 24 B P P