ASYNCHRONOUS TO SYNCHRONOUS CONVERTER Search Results

AN943

Abstract: remote control receiver rx 6p g rx 6p g receiver MC145422 MC145425 MC145428P AN946 EIA-232 MC145421 MC145426
Contextual Info: ML145428 Asynchronous–to–Synchronous and Synchronous–to– Asynchronous Converter Legacy Device: Motorola MC145428 The ML145428 Data Set Interface provides asynchronous-to-synchronous and synchronous-to-asynchronous data conversion. It is ideally suited for

rx 6p g receiver

Abstract: AN943 AN946 EIA-232 MC145421 MC145422 MC145425 MC145426 MC145428 ML145428
Contextual Info: ML145428 Asynchronous–to–Synchronous and Synchronous–to– Asynchronous Converter Legacy Device: Motorola MC145428 The ML145428 Data Set Interface provides asynchronous-to-synchronous and synchronous-to-asynchronous data conversion. It is ideally suited for

78105

Contextual Info: MAS7838 SIGNAL H H O C tS S IN G EXCELLENCE CMOS Asynchronous to Synchronous Converter • Interfaces an asynchronous channel to a synchronous channel ■ Implements CCITT recommendation V.22 ■ 64 kbit/s transmission rate ■ 25mW typical power dissipation

marking code ASY

Abstract: MAS7838 MAS9138 MAS9138N MAS9138S TDI timing Crystal Oscillator TXC
Contextual Info: DA9138.003 29 January, 2001 MAS9138 ASYNCHRONOUS TO SYNCHRONOUS CONVERTER • Pin compatible with MAS7838 • Interfaces a duplex asynchronous to synchronous channel • Modem speeds of 600, 1.2k, 2.4k, 4.8k, 7.2k, 9.6k, 12k, 14.4k, 19.2k and 38.4k bps with a single 4.9152 MHz crystal

XR-2122

Contextual Info: Z * E X 4 XR-2124 R Universal Data Buffer FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The X R -2 1 24 is a logic circuit designed to perform the data buffer function for modem systems. Both asynchronous to synchronous and synchronous to asynchronous conversion

XR-2135A

Abstract: 2135acp BPS-8 equivalent XR-2135ACN XR-2135ACP MISSING PULSE DETECTOR CIRCUIT XR-2135
Contextual Info: XR-2135A XR-2135A CCITT Data Buffer GENERAL DESCRIPTION PIN ASSIGNMENT The XR-2135A is a digital circuit designed to perform the function of data buffering for various serial data systems, including modems. Both the asynchronous- to-synchronous TXEN conversion and the synchronous-to- asynchronous

Contextual Info: 74HC/HCT166 MSI 8-BIT PARALLEL-IN/SERIAL-OUT SHIFT REGISTER FEA TU RES T Y P IC A L • Synchronous parallel-to-serial applications • Synchronous serial data input for easy expansion Clock enable for “ do nothing" mode Asynchronous master reset For asynchronous parallel data load

CD74HC40103-EP

Contextual Info: CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 D Qualified for Automotive Applications D Synchronous or Asynchronous Preset D Cascadable in Synchronous or Ripple D D VCC Voltage = 2 V to 6 V

5mm ldr

Abstract: 5mm ldr datasheet 2V06 LDR 5mm LDR SPECIFICATION LM2655 LM2655MTC-ADJ LM2655MTCX-ADJ MTC16 TSSOP-16
Contextual Info: LM2655 2.5A High Efficiency Synchronous Switching Regulator General Description Features The LM2655 is a current-mode controlled PWM step-down switching regulator. It has the unique ability to operate in synchronous or asynchronous mode. This gives the designer flexibility to choose between the high efficiency of

Contextual Info: INTEGRATED TOSHIBA CIRCUIT TECHNICAL TO SH IBA C M O S DIGITAL INTEGRATED CIRCUIT TC74ACT161P/F/FN, TC74ACT163P/F/FN DATA SILICON M O N O LITHIC SYNCHRONOUS PRESETTABLE 4 -B IT BINARY COUNTER TC74ACT161 P/F/FN ASYNCHRONOUS CLEAR TC74ACT163P/F/FN SYNCHRONOUS CLEAR_

CD74HC40103-EP

Contextual Info: CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 D VCC Voltage = 2 V to 6 V D High Noise Immunity NIL or NIH = 30% of D Qualified for Automotive Applications D Synchronous or Asynchronous Preset

SYM53C141

Abstract: SYM53C120 SYM53C895 lsi gigablaze transceiver LT/SG3527A
Contextual Info: SYM53C141 Data Sheet SYM53C141 LVD SCSI Bus Ex pander Features Ÿ Attaches single-ended SCSI devices to a Low Voltage Differential LVD SCSI bus Ÿ Accepts any asynchronous or synchronous transfer speed up to Ultra SCSI Ÿ Operates as a SCSI Bus Converter or Repeater

Contextual Info: LSI LOGIC SYM53C141 Data Sheet SYM53CI4I LVD SCSI Bus Expander Features • Attaches single-ended SCSI devices to a Low Voltage Differential LVD SCSI bus • Accepts any asynchronous or synchronous transfer speed up to Ultra SCSI • Operates as a SCSI Bus Converter or Repeater

SN54HC193

Abstract: SN74HC193 SN74HC193-Q1 SN74HC193QPWRG4Q1 SN74HC193QPWRQ1
Contextual Info: SN74HC193ĆQ1 4ĆBIT SYNCHRONOUS UP/DOWN COUNTER DUAL CLOCK WITH CLEAR SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008 D D D D D D D D D Fully Synchronous in Count Modes D Parallel Asynchronous Load for Modulo-N Qualified for Automotive Applications Wide Operating Voltage Range of 2 V to 6 V

Contextual Info: SN54ALS569A, SN74ALS568A, SN74ALS569A SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS SDAS229A – APRIL 1982 – REVISED JANUARY 1995 The clear function is initiated by applying a low level to either asynchronous clear ACLR or

HEF4021

Contextual Info: HEF4021B 8-bit static shift register Rev. 8 — 18 November 2011 Product data sheet 1. General description The HEF4021B is an 8-bit static shift register parallel-to-serial converter with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH

HEF4021B

Abstract: HEF4021BP HEF4021BT JESD22-A114E
Contextual Info: HEF4021B 8-bit static shift register Rev. 04 — 10 November 2008 Product data sheet 1. General description The HEF4021B is an 8-bit static shift register parallel-to-serial converter with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH

Contextual Info: SN54ALS569A, SN74ALS568A, SN74ALS569A SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS SDAS229A – APRIL 1982 – REVISED JANUARY 1995 The clear function is initiated by applying a low level to either asynchronous clear ACLR or

ndf 020-21

Contextual Info: T1Mx28 Device DS1 Mapper 28-Channel TXC-04228 TECHNICAL OVERVIEW PRODUCT PREVIEW DESCRIPTION FEATURES The T1Mx28 is a 28-channel byte-synchronous and asynchronous DS1 mapper. Four field-proven DS1MX7 DS1 Mapper chips are interconnected in a single compact package to

Contextual Info: SN54ALS569A, SN74ALS568A, SN74ALS569A SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS SDAS229A – APRIL 1982 – REVISED JANUARY 1995 The clear function is initiated by applying a low level to either asynchronous clear ACLR or

Contextual Info: SN54ALS569A, SN74ALS568A, SN74ALS569A SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS SDAS229A – APRIL 1982 – REVISED JANUARY 1995 The clear function is initiated by applying a low level to either asynchronous clear ACLR or

sn74als569an

Contextual Info: SN54ALS569A, SN74ALS568A, SN74ALS569A SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS SDAS229A – APRIL 1982 – REVISED JANUARY 1995 The clear function is initiated by applying a low level to either asynchronous clear ACLR or

Contextual Info: SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS246G – AUGUST 1993 – REVISED APRIL 1998 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Synchronous Read-Retransmit Capability

Contextual Info: SN74ACT3651 2048 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS439D – JUNE 1994 – REVISED FEBRUARY 1999 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Synchronous Read-Retransmit Capability