ASYNCHRONOUS ENGINE SPEED CONTROL Search Results

AMBA APB UART

Abstract: dlc10 UT699 352-CQFP state machine for ahb to apb bridge AMBA AHB memory controller UT699 memory map UT699 cpci driver ahb fsm SDRAM edac
Contextual Info: UT699 32-bit Fault-Tolerant LEON 3FT/SPARCTM V8 Processor Aeroflex Colorado Springs 800-645-8862 www.aeroflex.com/LEON August 2009 UT699 LEON 3FT Description T Operates from 3.3V for I/O and 2.5V for core T Multifunctional memory controller supports PROM, SRAM, SDRAM, and I/O

MAX232 to rj45

Abstract: KSZ8041FTL KSZ8995MA KSZ8893MQL application note KSZ8041TL KSZ8995XA KSZ8999 micrel ksz8993m 8051 MAX232 interface max232 to rj45 flash
Contextual Info: Ethernet Applications 1 Stand Alone Un-Managed Switch KSZ8995XA Queue Mgmnt Buffer Mgmnt Frame Buffers MIB Counters EEPROM I/F SPI Control Registers SWITCH, VLAN, QOS, Flow Rate Control 1K Look-Up Engine MAC1 PHY1 MAC2 PHY2 MAC3 PHY3 MAC4 PHY4 MAC5 PHY5 2

verilog code for dma controller

Abstract: verilog code for ahb bus slave CW000026
Contextual Info: USB-High Speed Multi-Port Host Controller CW000026 USB 2.0 HIGH SPEED CONTROLLER PORTFOLIO FEATURES The CoreWare CW000026 Multi-Port Host MPH core is a highly optimized, low gate count IP core that allows system developers to implement compact, cost effective, low power USB-based SoC solutions.

MSM13R0000

Abstract: MSM98R000 W712
Contextual Info: Technical Brief O K I A S I C P R O D U C T S W712 Universal Serial Bus Controller 0.5µ m Technology Mega Macrofunction January 1997 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

ATA hard disk controller

Abstract: HARD DISK diagram RD1095
Contextual Info: IDE/ATA Interface Controller with WISHBONE June 2010 Reference Design RD1095 Introduction Integrated Drive Electronics IDE is one of the most popular data bus interfaces for PCs. The IDE interface links a computer motherboard’s data paths to the computer’s disk storage devices. This interface is known by many different names including ATA, ATA/ATAPI, and EIDE. Although the IDE controller is built into the hard drive, an interface

microcontroler

Contextual Info: Serial Interface Engine Support full speed devices Extraction clock and data signals in internal DPLL CUSB NRZI decoding/encoding USB 1.1 Device Controller Core Bit stuffing/stripping CRC checking/generation Interface for an external transceiver Up to 31 configurable endpoints

ddr3 ram

Abstract: MPC8569E PIC interface SD MMC LTE Receiver ddr3 power controller i2c
Contextual Info: Integrated Communication Processors MPC8569E PowerQUICC III Processor Overview The MPC8569E PowerQUICC® III family is designed to address the increasing performance requirements for broadband access equipment including 3G/WiMAX/LTE base stations, radio network controllers,

Evatronix CUSB

Abstract: nrzi encoding in usb ProASIC3 CUSB
Contextual Info: Serial Interface Engine o Support full speed devices o Extraction clock and data sig- nals in internal DPLL CUSB o NRZI decoding/encoding Universal Serial Bus Device Controller Core o Bit stuffing/stripping o CRC checking/generation o Interface for an external

ep3C5

Abstract: R8051XC
Contextual Info:  Support for Full and Low Speed operation according to the USB 2.0 specification  Generic system bus interface USBFS-DEV  Serial Interface Engine USB Full-Speed Device Controller Megafunction Support full speed devices Extraction clock and data signals

R8051XC

Abstract: usbfs-5 3S1600E
Contextual Info:  Support for Full and Low Speed operation according to the USB 2.0 specification  Generic system bus interface USBFS-DEV  Serial Interface Engine USB Full-Speed Device Controller Core  Support full speed devices  Extraction clock and data sig-

MPC8568E

Abstract: Pico BTS of 3g ATM8 MPC8567E SHA12 "network interface cards"
Contextual Info: Integrated Host Processors MPC8568E PowerQUICC III Processor Overview MPC8568E Family Block Diagram integrated Control and Data Path for Network Interface Cards The MPC8568E PowerQUICC™ III family e500 core is designed to address the increasing 32 KB I-Cache

8-bit counter VERILOG

Abstract: 80C31 ASM51 D80530 DS80C320 Memory Management 8051 Programmable interval timer chips 80c31 interface vhdl synchronous parallel bus microcontroller 8051 program of alarm clock
Contextual Info: 8-bit Control Unit 8-bit Arithmetic-Logic Unit 32-bit Input/Output ports D80530 8-bit Microcontroller Core Three 16-bit Timer/Counters Two Serial Peripheral Interfaces in full duplex mode Three priority/Fourteen source Interrupt Controller 27-bit Programmable Watchdog

OS8104

Abstract: sony unilink bus OS8104AQ sony unilink pinout OS8104AQR f os8104 Oasis SiliconSystems AG oasis Oasis SiliconSystems DS8104PP2
Contextual Info: MOST Media Oriented Systems Transport Multimedia and Control Networking Technology OS8104 Preliminary Product Data Sheet DS8104PP2 Sept. 2000  Copyright 1997-2000 Oasis SiliconSystems AG OS8104 Ordering Information OS8104gpR R - Tape and Reel optional

Contextual Info: SMC SM C91C100 STANDARD MICROSYSTEMS CORPORATION FEAST Fast Ethernet Controller FEATURES • • • • • • • • SMSCS001 Dual Speed C S M A /C D Engine 10 Mbps and 100 Mbps Compliant w ith IEEE 8 0 2 .3 100BASE-T Specification Supports 100BASE-TX, 100BASE-T4, and

DP83256

Abstract: DP83257 DP83261 DP83265 DP83266 AB8p DP83266 MACSI Device MAC layer sequence number
Contextual Info: NATL SEHICON]> LINEAR (□501124 QQÖ334S H2S bbE ]> PRELIMINARY DP83266 MACSI Device (FDDI Media Access Controller and System Interface) On-chip address bit swapping capability 32-bit wide Address/Data path with byte parity Programmable transfer burst sizes of 4 or 8

SiS968

Abstract: SiSM671MX SiS chipset south bridge SIS SiSM671 lcd tv controller DDR2-667 new sis chip
Contextual Info: Product Info - SiSM671MX The Integrated Mirage 3 DX 9 Graphics Chipset for Intel Pentium® M Overview The SiSM671MX, supporting Pentium® M series processor, features a PCI Express x16 Bridge, flexible Single-Channel DDR2-667 Memory controller, Mirage™ 3 graphic engine, and SiS MuTIOL® Technology,

NetLogic

Abstract: NetLogic Microsystems network search engine netlogic longest prefix matching algorithm code NFA 10G verilog code for longest prefix matching invalid opcode netlogic "application note" longest prefix matching algorithm cidr
Contextual Info: Application Note NCS018 July 2000 A Basic Controller for the CIDR Co-Processor Longest Prefix Match Engine Introduction The NL77542 CIDR Co-Processor™ Longest Prefix Match Engine is a table lookup engine optimized for the Longest Prefix Match search algorithm used in Classless Inter-Domain Routing RFC1519 . By

IEC60958

Abstract: I2S serial bus protocol BT601 IEC-60958 BT.601 parking aid IEEE-1394b-2008 MB88395 4096B IEC-61883
Contextual Info: 1394 Automotive Single Chip Controller MB88395 and MB88389 400Mbps 800Mbps In-vehicle entertainment MB88395 BT.601 SmartCODEC 800Mbps and SoC 3.2Gbps and SoC MB8839x * BT.601 Audio SmartCODEC 2ch 2ch BT.601 Audio SmartCODEC 2ch 2ch DTCP Audio DTCP LINK 800Mbps PHY

R8051XC

Abstract: TSMC 90nm 80C51 R8051XC2
Contextual Info: Support for Full and Low Speed operation according to the USB 2.0 specification USBFS-DEV USB Full-Speed Device Controller Core Generic system bus interface Serial Interface Engine o Support full speed devices o Extraction clock and data sig- nals in internal DPLL

SN2681

Abstract: mips r3000 pin diagram R3001 R3010 mips processor SCN2681 3 pins Variable resistor 10K ohm Sn268 PB-104
Contextual Info: SP'X R3001 RISC ENGINE FOR EMBEDDED CONTROLLERS Jdfj ADVANCE INFORMATION IDT7RS104 Integrated De>rice Technology, Inc. R3001 MODULE WITH SYNCHRONOUS MEMORY FEATURES: • 128K each of Instruction and Data RAM In Synchronous Memory • Simple Interface to peripherals

XC95108PC84

Abstract: Engineering Design Automation reference design GTS 250 ts08 PC84 TS01 XC2064 XC3090 XC4005 XC7000
Contextual Info: ON LIN E R XEPLD REFER E NCE G UI DE FOR WINDOWS TABL E OF CONT ENT S INDEX GO T O OT HER BOOKS 0 4 0 1306 XEPLD Reference Guide Design Flow Using the Design Manager Controlling Design Implementation Controlling Design Timing Timing Analysis R XEPLD Reference Guide

design of dma controller using vhdl

Abstract: GT-64111 E1 TO Ethernet-MAC using vhdl 4321 display CMOS DIGITAL CAMERA 640x480 colour tv kit circuit diagram E1 PCM encoder Ethernet-MAC E1 using vhdl GALILEO TECHNOLOGY interface of rs232 to UART in VHDL
Contextual Info: IDT Support Components Support Components Section 8 189 Support Components Galileo Technology, Inc. GT-64010A: System Controller with PCI Interface for RC4650/4700/5000/64475 CPUs Features Description ◆ Integrated system controller with 32-bit PCI bus interface

pcI diagnostic card codes

Abstract: usb host mp3 decoder ic high speed parallel to usb IC connector debug codes usb pci NET2888 "USB" peripheral fingerprint scanner circuit netchip pioneer dvd player pioneer pll
Contextual Info: NetChip NET2290 32-Bit USB 2.0 Programmable Peripheral Controller Overview NetChip’s NET2290 USB 2.0 programmable peripheral controller continues to set the standard as the highest performance device chip on the market. NET2290 provides significant feature enhancements to NetChip’s current USB

weitek power 9000

Abstract: W5186 weitek weitek bitblt ai-230 vesa local bus vesa local bus design weitek 9000 DRAM 64kx16
Contextual Info: POWER 9000 USER INTERFACE CONTROLLER October 1992 Chapter 1. Features 2-D G RA PH ICS A C C E LE R A T O R Supports polylines and mesh polygons for faster drawing Single-chip controller Supports pick mode Accelerates M icrosoft Windows and AutoCAD Supports resolutions up to 1600x1200x8, 1280x1024x8,