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AMD Xilinx XC3S1600E-5FG320C FPGA Spartan®-3EFamily 1.6MGates 33192Cells 657MHz 1.2V 320-Pin FBGA Tray
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Bristol Electronics	XC3S1600E-5FG320C		168			1 - 10 - 100 - 1000 - 10000 -	Get Quote
AMD Xilinx XC3S1600E-5FGG484C FPGA Spartan®-3EFamily 1.6MGates 33192Cells 657MHz 1.2V 484-Pin FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Bristol Electronics	XC3S1600E-5FGG484C		19			1 - 10 - 100 - 1000 - 10000 -	Get Quote
AMD Xilinx XC3S1600E-4FGG400C FPGA Spartan®-3EFamily 1.6MGates 33192Cells 572MHz 1.2V 400-Pin FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Bristol Electronics	XC3S1600E-4FGG400C		18			1 - 10 - 100 - 1000 - 10000 -	Get Quote
AMD Xilinx XC3S1600E-4FG484C FPGA Spartan®-3EFamily 1.6MGates 33192Cells 572MHz 1.2V 484-Pin FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Bristol Electronics	XC3S1600E-4FG484C		16			1 - 10 - 100 - 1000 - 10000 -	Get Quote
AMD Xilinx XC3S1600E-4FG320C FPGA Spartan®-3EFamily 1.6MGates 33192Cells 572MHz 1.2V 320-Pin FBGA Tray
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Bristol Electronics	XC3S1600E-4FG320C		14			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Vyrian	XC3S1600E-4FG320C		3,440			1 - 10 - 100 - 1000 - 10000 -	Get Quote

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3S1600E Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
C3202 Abstract: C32025 TMS320C25 test bench for 16 bit shifter C32025TX Contextual Info: Control Unit o 16-bit instruction decoding o Repeat instructions for effi- C32025 Digital Signal Processor Core cient use of program space and enhanced execution Central Arithmetic-Logic Unit o 16-bit parallel shifter; 32-bit arithmetic and logical operations	Original	16-bit c32025 32-bit tms320c25 +3c3202 test bench for 16 bit shifter c32025tx	PDF
6SLX25-2 Abstract: 3s1000-5 SPARTAN-6 image processing 3S100 DSP48A DSP48E 6SLX25 "motion jpeg" dcm verilog code Contextual Info: Baseline ISO/IEC 10918-1 JPEG Compliance Programmable Huffman Tables two DC, two AC and JPEG-D Programmable quantization tables (four) Baseline JPEG Decoder Core Up to four color components (optionally extendable to 255 components) Supports all possible scan configurations and all JPEG formats	Original	1920x1152 6slx25-2 3s1000-5 spartan-6 image processing +63s100 dsp48a dsp48e 6slx25 motion jpeg dcm verilog code	PDF
6SLX150-2 Abstract: verilog code for dma controller synchronous fifo design in verilog interrupt controller verilog code 6SLX150 6VCX240-2 verilog hdl code for programmable peripheral interface Contextual Info: Full compliance with the USB 2.0 specification USBHS-DEV High Speed USB Device Controller Core The USBHS-DEV core implements a complete high/full-speed 480/12 Mbps peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a system’s	Original	6slx150-2 verilog code for dma controller synchronous fifo design in verilog interrupt controller verilog code +36slx150 6vcx240-2 verilog hdl code for programmable peripheral interface	PDF
verilog code for 32 bit AES encryption Abstract: SP800-38A FIPS-197 3S1600E Contextual Info:  Conforms to the Advanced En- cryption Standard AES standard (FIPS PUB 197) AES-P  Single module efficiently inte- Programmable AES Encrypt/Decrypt Core  Run-time programmable for: grates multiple AES functions and modes − Encryption or Decryption	Original	fips-197 128-bit 192-bit 256-bit +3verilog code for 32 bit aes encryption sp800-38a 3s1600e	PDF
verilog code for huffman coding Abstract: 3S1500 Contextual Info: Baseline ISO/IEC 10918-1 JPEG Compliance  Programmable Huffman Tables JPEG-C Baseline JPEG Codec Core two DC, two AC and  Programmable quantization tables (four)  Up to 4 color components (op- tionally extendable to 255 components)  Supports all possible scan confi-	Original	verilog code for huffman coding 3s1500	PDF
R8051XC Abstract: usbfs-5 3S1600E Contextual Info:  Support for Full and Low Speed operation according to the USB 2.0 specification  Generic system bus interface USBFS-DEV  Serial Interface Engine USB Full-Speed Device Controller Core  Support full speed devices  Extraction clock and data sig-	Original	8/16/24/32-bit 8/16/32-bit r8051xc usbfs-51 +2usbfs-5 3s1600e	PDF
XAPP1055 Abstract: UART16550 flexray PROTOCOL microblaze XA3S1600E X300 bus guardian configuration registers of flexray c automotive ecu UART-16 3S1600E Contextual Info: Application Note: Reference System - XPS FlexRay Controller Reference System: FlexRay Using the XA Automotive ECU Development Kit R XAPP1055 v1.0 April 25, 2008 Abstract This application note describes a reference system that tests the operation of the Xilinx	Original	xapp1055 xa3s1600e uart16550 flexray protocol +6microblaze x300 bus guardian configuration registers of flexray c automotive ecu uart-16 3s1600e	PDF
verilog code for des Abstract: verilog code for implementation of des inverse quick transformation 0123456789ABCDEF A28E91724C4BBA31 Contextual Info: FIPS 46-3 Standard Compliant Encryption/Decryption performed in 48 cycles ECB mode DES3 Up to 168 bits of security Triple Data Encryption Standard Core Verilog IP Core The DES3 core implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.	Original	verilog code for des verilog code for implementation of des inverse quick transformation 0123456789abcdef +1a28e91724c4bba31	PDF
CTXIL206 Abstract: vhdl code for multiplexing MPEG2 sd card interfacing spartan 3E FPGA RX 3E vhdl code for multiplexing table dvb-t XAPP1015 vhdl code for spartan 6 audio vhdl code for multiplexing Tables in dvb-t vhdl code for dvb-t 2 YCbCr output LVDS Contextual Info: Audio/Video Connectivity Solutions for Spartan-3E FPGAs Reference Designs for the Broadcast the Broadcast Industry: Volume 3 Industry: Volume 3 [optional] XAPP1015 v1.0 September 28, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development	Original	xapp1015 ctxil206 vhdl code for multiplexing mpeg2 sd card interfacing spartan 3e fpga +6rx 3e vhdl code for multiplexing table dvb-t vhdl code for spartan 6 audio vhdl code for multiplexing tables in dvb-t vhdl code for dvb-t 2 ycbcr output lvds	PDF
D-Sub 44-pin male Connector Abstract: XA3S1600E 44PIN male connector Xilinx jtag cable Schematic Xilinx usb cable Schematic D-SUB-44 automotive ecu UART16550 X300 XAPP1056 Contextual Info: Application Note: Reference System XPS CAN Controller Reference System: CAN Using the XA Automotive ECU Development Kit R XAPP1056 v1.0 April 25, 2008 Abstract This application note describes a reference system to test the operation of Xilinx Platform Studio (XPS) Controller Area Network (CAN) cores that are connected to each other using	Original	xapp1056 xa3s1600e d-sub 44-pin male connector 44pin male connector +6xilinx jtag cable schematic xilinx usb cable schematic d-sub-44 automotive ecu uart16550 x300	PDF
c80186 Abstract: 80186EC Intel 80c86 block diagram 8259A 16X16 80C186EC C80187 186EC intel FPGA 80C186EC Contextual Info: Control Unit: − 9-level deep and 1-byte wide instruction queue C80186EC 80186EC-Compliant Chip Replacement 16-bit Microcontroller Core − Independent instruction ex- ecution stages allow instructions to overlap Arithmetic Logic Unit: − 16-bit arithmetic and logical	Original	c80186ec 80186ec-compliant 16-bit 80c186ec +1080186ec 80c86 80c186 c80186 intel 80c86 block diagram 8259a 16x16 c80187 186ec intel fpga 80c186ec	PDF
verilog code for ddr2 sdram to virtex 5 Abstract: ddr phy 5VLX30-3 Contextual Info: DDR2-SDRAM-CTRL DDR/DDR2 SDRAM Memory Controller Core The DDR2-SDRAM-CTRL core provides a simplified, pipelined, burst-optimized interface to all industry-standard DDR and DDR-II SDRAM devices currently available, including Mobile DDR SDRAMs. It features:	Original	3s1600e-5 2v1000-6 4vlx25-12 5vlx30-3 +2verilog code for ddr2 sdram to virtex 5 ddr phy	PDF
verilog code for 128 bit AES encryption Abstract: 3s250e SP800-38A FIPS-197 nist SP800-38A Contextual Info: Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) AES-C Single module efficiently integrates multiple AES functions AES Optimized Encrypt/Decrypt Core Run-time programmable for: The AES-C core implements hardware data encryption and decryption using Rijndael	Original	fips-197 256-bits sp800-38a verilog code for 128 bit aes encryption +23s250e nist sp800-38a	PDF
automotive ecu Abstract: XAPP1054 XA3S1600E DS638 UART16550 X300 microblaze 3S1600E Contextual Info: Application Note: Reference System XPS MOST NIC Controller Reference System: MOST NIC Using the XA Automotive ECU Development Kit R XAPP1054 v1.0 April 25, 2008 Abstract This application note describes a reference system that tests the operation of the Xilinx	Original	xapp1054 xa3s1600e automotive ecu ds638 +4uart16550 x300 microblaze 3s1600e	PDF