ASM5P2305 Search Results

Contextual Info: ASM5P2309A ASM5P2305A October 2003 rev 1.0 3.3V Zero Delay Buffer General Features • parts have on-chip PLLs that lock to an input clock on the REF 10 MHz to 133- MHz operating range, compatible with CPU and PCI bus frequencies. • Zero input - output propagation delay.

Contextual Info: PCS3P624Z05B/C and PCS3P624Z09B/C High Frequency Timing-Safe Peak EMI Reduction IC General Features • High Frequency Clock distribution with Timing-Safe™ Peak EMI Reduction • Input frequency range: 50MHz - 100MHz • Multiple low skew Timing-safe™ Outputs:

Contextual Info: PCS3P624Z05B, PCS3P624Z05C, PCS3P624Z09B, PCS3P624Z09C Product Preview High Frequency TIMING SAFEt Peak EMI Reduction IC Description PCS3P624Z05/09 is a versatile, 3.3 V Zero−delay buffer designed to distribute high frequency Timing−Safe clocks with Peak EMI

ASM5P2305A

Contextual Info: PCS3P623Z05A/B PCS3P623Z09A/B May 2008 rev 0.1 Timing-Safe Peak EMI reduction IC designed to distribute Timing-Safe™ clocks with Peak EMI General Features • reduction. PCS3P623Z05 is an eight-pin version, accepts Clock distribution with Timing-Safe™ Peak EMI

ASM5P2305A

Contextual Info: PCS3P625Z05B/C PCS3P625Z09B/C May 2008 rev 0.1 High Frequency Timing-Safe Peak EMI reduction IC with Peak EMI reduction. PCS3P625Z05 is an eight-pin General Features • version, accepts one reference input and drives out five High Frequency Clock distribution with TimingSafe™ Peak EMI Reduction