AN46982 Search Results

Contextual Info: PLL Considerations in QDRII/II+/DDRII/II+SRAMs AN46982 Author: Jayasree Nayar Associated Project: No Associated Part Family: CY7C1*KV18,CY7C2*KV18 Software Version: NA Associated Application Notes: None Application Note Abstract AN46982 provides an overview of the Phase Locked Loop PLL and describes its operation in PLL disabled mode in

Contextual Info: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions