AN1108 Search Results

DisplayPort PCB layout guidelines

Contextual Info: AN11082 PCB design and layout guidelines for CBTL04083A/CBTL04083B Rev. 1 — 22 July 2011 Application note Document information Info Content Keywords high-speed signal, PCB, layout, loss, jitter Abstract This document provides a practical guideline for PCB design and layout in

ENC28J50

Abstract: AN1108 DHCP enc28j60 ENC28J60 setsockopt ENC28J60-H Thermistor project AN833 PIC32 BFR25
Contextual Info: AN1108 Microchip TCP/IP Stack with BSD Socket API Author: Abdul Rafiq Microchip Technology Inc. INTRODUCTION The Microchip TCP/IP Stack with BSD Berkley Socket Distribution Socket API provides the socket library for Internet TCP/IP communications. The generic socket

AN1108

Abstract: FETs Field Effect Transistors Epad Product ALD1108E ALD1110E ALD1702 EA101 EA102 ALD1106
Contextual Info: ADVANCED LINEAR DEVICES, INC. APPLICATION NOTE AN1108 ELECTRICALLY PROGRAMMABLE ANALOG DEVICE EPAD APPLICATIONS INTRODUCTION The ALD1108E/ALD1110E are the first members in a growing family of Electrically Programmable Analog Device (EPAD) integrated circuits from Advanced Linear Devices.

Contextual Info: AN11089 RD70x Driver Installation Guide for Windows 7 Rev. 1.3 — 28 August 2012 211713 Application note COMPANY PUBLIC Document information Info Content Keywords CL RD70x series, Windows 7 Quick startup guide, Pegoda reader Abstract This document is intended for users starting to work with the Pegoda

Contextual Info: AN11084 Very large I2C-bus systems and long buses Rev. 1 — 14 October 2011 Application note Document information Info Content Keywords I2C-bus, twisted pair cables, very long buses, communication cables, Cat5e, Cat6, Fast-mode, Fast-mode Plus, Fm+, inter-IC, SDA, SCL, P82B96,

MURATA GRM15 -V2

Contextual Info: AN11086 BGU7003 LNA application for GPS L2 band Rev. 2 — 9 October 2012 Application note Document information Info Content Keywords BGU7003, LNA, GPS L2 band. Abstract This application note provides circuit simulation, schematic, layout, BOM and typical EVB performance for GPS L2 LNA based on BGU7003.

Contextual Info: DS90CR486 www.ti.com SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013 DS90CR486 133MHz 48-Bit Channel Link Deserializer 6.384 Gbps Check for Samples: DS90CR486 FEATURES 1 • • • • • • 2 • • • • • Up to 6.384 Gbps Throughput 66MHz to 133MHz Input Clock Support

Contextual Info: DS92LV1260 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Literature Number: SNLS134E DS92LV1260 Six Channel 10 Bit BLVDS Deserializer General Description Features The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to

Contextual Info: DS90CR287,DS90CR288A DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz Literature Number: SNLS056F DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/

M16A

Abstract: RG-142 DS90CP22 DS90CP22M-8 HP70841B
Contextual Info: DS90CP22 2X2 800 Mbps LVDS Crosspoint Switch General Description Features DS90CP22 is a 2x2 crosspoint switch utilizing LVDS Low Voltage Differential Signaling technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width

DS90CR283

Abstract: DS90CR283MTD DS90CR284 DS90CR284MTD MTD56
Contextual Info: DS90CR283/DS90CR284 28-Bit Channel Link-66 MHz General Description The DS90CR283 transmitter converts 28 bits of CMOS/TTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every

Contextual Info: DS90CR483A, DS90CR484A www.ti.com SNLS291A – APRIL 2008 – REVISED APRIL 2013 DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz Check for Samples: DS90CR483A, DS90CR484A FEATURES 1 • • • 2 • • • • • • • • •

Contextual Info: DS90CR481, DS90CR482 www.ti.com SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013 DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz Check for Samples: DS90CR481, DS90CR482 FEATURES 1 • • • • 2 • • • • • • • • 3.168 Gbits/sec Bandwidth with 66 MHz Clock

LVDS to MIPI CSI

Abstract: LVDS to mipi bridge MIPI csi-2 mipi csi-2 receiver mipi csi receiver MIPI D-PHY mipi csi-2 transmitter MIPI csi bridge 400x240 MIPI csi-2 receivers
Contextual Info: DS90UR910Q 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter General Description Features The DS90UR910Q is an interface bridge chip that recovers data from the FPD-Link II serial bit stream and converts into a Camera Serial Interface CSI-2 format compatible with Mobile Industry Processor Interface (MIPI) specifications. It recovers the 24- or 18-bit RGB data and 3 video sync-signals

Contextual Info: D S90LV001 DS90LV001 800 Mbps LVDS Buffer Texas In s t r u m e n t s Literature Number: SNLS067D £/r Semiconductor DS90LV001 800 Mbps LVDS Buffer General Description An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

Contextual Info: D S99R 124Q DS99R124Q 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter Texa s In s t r u m e n t s Literature Number: SNLS318C t D S 99R 124Q Sem iconductor 5 - 4 3 M H z 18-bit C o lo r F P D -L in k II to F P D -L in k C o n ve rte r Features

Contextual Info: J t / i Texas " DS90UR907Q In s t r u m e n t s 5 - 6 5 MHz 24-bit Color FPD-Link to FPD-Link II Converter Features S 5 ± 65 MHz support 140 Mbps to 1.82 Gbps Serial Link Serial transmission is optimized by a user selectable de-emphasis and differential output level select features. EMI is

DS90UB926

Abstract: DS90Ub926Q SNLS407 LVDS 35-bit SSC
Contextual Info: DS90UB925Q 5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel General Description Features The DS90UB925Q serializer, in conjunction with the DS90UB926Q deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio,

Contextual Info: DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DS90LV001 800 Mbps LVDS Buffer Check for Samples: DS90LV001 FEATURES DESCRIPTION • • • • • • The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In

Contextual Info: DS92LV090A DS92LV090A 9 Channel Bus LVDS Transceiver Literature Number: SNLS025C DS92LV090A 9 Channel Bus LVDS Transceiver General Description Features The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from

DS90LV110

Abstract: DS90LV110T DS90LV110TMTC RG-142
Contextual Info: DS90LV110T 1 to 10 LVDS Data/Clock Distributor General Description Features DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS Low Voltage Differential Signaling technology for low power, high speed operation. Data paths are fully differential

DS90CR287

Abstract: DS90CR287MTD DS90CR288 DS90CR288MTD MTD56 LVDS 30 pin connector cable signal path designer
Contextual Info: DS90CR288 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Receiver - 75 MHz General Description Features The DS90CR287 see DS90CR287/288A datasheet transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phaselocked transmit clock is transmitted in parallel with the data

DS90CR217

Abstract: DS90CR217MTD DS90CR218A DS90CR218AMTD MTD48
Contextual Info: DS90CR217/DS90CR218A +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz General Description Features The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in

AEC-Q100

Abstract: automotive ecu manual "parking sensor" MCU
Contextual Info: DS90UB901Q/DS90UB902Q 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel General Description The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single