AMD 9512 Search Results

AC97

Abstract: MK1491-06 MK1491-06R MK1491-06RLF MK1491-06RTR SEL24
Contextual Info: MK1491-06 AMD Geode Clock Source Description Features The MK1491-06 is a low-cost, low-jitter, high-performance clock synthesizer for AMD’s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked Loop PLL techniques, the device accepts a 14.318

Contextual Info: MK1491-06 AMD Geode Clock Source Description Features The MK1491-06 is a low-cost, low-jitter, high-performance clock synthesizer for AMD’s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked Loop PLL techniques, the device accepts a 14.318

MARKING 09F

Contextual Info: MK1491-09 AMD Geode GX2 Clock Source Description Features The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD’s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked Loop PLL techniques, the device accepts a 14.318

MK1491-09

Contextual Info: MK1491-09 AMD Geode GX2 Clock Source Description Features The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD’s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked Loop PLL techniques, the device accepts a 14.318

011106

Contextual Info: MK1491-09 AMD Geode GX2 Clock Source Description Features The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD’s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked Loop PLL techniques, the device accepts a 14.318

Contextual Info: MK1491-09 AMD Geode GX2 Clock Source Description Features The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD’s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked Loop PLL techniques, the device accepts a 14.318

Contextual Info: MK1491-09 AMD Geode GX2 Clock Source Description Features The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD’s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked Loop PLL techniques, the device accepts a 14.318

winbond 25080

Abstract: 29F200BB 16LF648A 89V51RD2 18f252 89S51 National SEMICONDUCTOR GAL16V8 29sf040 12f675 29F400BB
Contextual Info: Dataman-S4 Version 3.00 <ALL> Devices List - 1. S4 8 bit EPROM lib. V3.00 - AMD 27010

AM85C30-10BQA

Abstract: Z8523010VEC Z8523016VEC AM85C30-10 AM85C30-8JI 85C30 AM85C30-10JI AM85C30-8JC Z85C3008PEC z85c3010vec
Contextual Info: White Paper AMD/ZiLOG Serial Communications Controller Comparisons WP000202-0102 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.961.1600 • Fax: 408.961.1800 • www.zilog.com White Paper Electrostatic Discharge

Firewire 800

Abstract: xilinx 1765 "Dual-Port RAM" Xilinx PCMCIA FPGA PCMCIA xilinx fpga
Contextual Info: 1394 SuperLINKCore Evaluation Board June 29, 1998 Product Specification • • • • Parallel Port interface Onboard AMD microcontroller Slot for 256K dual-port RAM Optional software drivers General Description Integrated Intellectual Property Inc. 1765 Scott Blvd. Suite 208

pSOS

Abstract: Lynx Real-Time Systems
Contextual Info: 3rd Party RTOS Software Vendors Supporting AMD Ethernet Controllers, February 1999 Company Name & Location Product Name PCnet-FAST, PCnet& uP Supported FAST+ PCnet-PCI II 32 PCnet-ISA II MACE Accelerated Technology Inc Nucleus-NET 720 Oak Circle Drive East

16L8L

Abstract: pal 22v10Q ecl pal 16 macrocells x6456 EPP-80
Contextual Info: 4.1 FIELD PROGRAMMABLE LOGIC SELECTOR GUIDE Features of PAL Devices Advantages of AMD PAL Devices • High speed electrically programmable array logic elements • User customizable logic patterns, generated in minutes with PROM type program­ mers • Improves performance and reduces board area and cost of existing TTL SSI/MSI

64 CERAMIC LEADLESS CHIP CARRIER LCC

Abstract: PD3024
Contextual Info: AmPAL*10H20EV8/AmPAL10020EV8 IMOX-III ECL Programmable Array Logic PRELIMINARY • • • • • High-performance tpo = 6 ns, fMAX - 125 MHz Eight user-programmable output logic m acrocells for registered or combinatorial operation A latched version of the d evice is available a s AmP A L1 0 H 2 0 E G 8 or A m P A L I 0 0 2 0 EG 8 se e AMD Publica­

RM0013

Abstract: MT28F008B3 PUG0016 0X800000
Contextual Info: eZ80Acclaim! MCUs Flash Library APIs Reference Manual RM001303-0306 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.zilog.com eZ80Acclaim!® MCUs Flash Library API Reference Manual

logos 4012B

Abstract: 1LB553 Rauland ETS-003 Silec Semiconductors MCP 7833 4057A transistor sr52 74c912 1TK552 74S485
Contextual Info: L p i > « , * S E m Ic O N VOLUM E 3 INTERNATIONAL INTEGRATED CIRCUITS INDEX 5th EDITION 1985 Revised June 1985 COMPILED AND PUBLISHED BY S E M IC O N IN D E X E S L IM IT E D THE SEMICON INDEX SERIES CONSISTS OF VOLUME 1 TRANSISTOR INDEX VOLUME 2 DIODE & SCR INDEX

JRC 45600

Abstract: YD 803 SGS 45600 JRC TDA 7277 TDA 5072 krp power source sps 6360 2904 JRC Sony SHA T90 SA philips HFE 4541
Contextual Info: I SEMICON INDEXES Contents and Introduction Manufacturers' Information V O LU M E 3 INTERNATIONAL INTEGRATED CIRCUITS INDEX 15th EDITION 1997 Numerical Listing of Integrated Circuits Substitution Guide U D C 621.382.3 Diagram s THE S E M IC O N INTERNATIONAL INDEXES

ecl pal 16 macrocells

Abstract: HD b3c
Contextual Info: AmPAL*10H20EG8/AmPAL10020EG8 IMOX-III ECL Programmable Array Logic PRELIMINARY Asynchronous-RESET and PRESET capability Power-up RESET capability PRELOAD for improved testability Special designed-ln test features for full AC and DC testing Platinum-silicide fuses ensure high programming yield,

Contextual Info: AmPAL*10H20EG8/AmPALI0020EG8 IMOX-III ECL Programmable Array Logic PRELIMINARY • • • • • High-performance tpp = 6 ns, fMAX = 125 MHz Eight user-programmable output logic macrocells for latched or combinatorial operation A registered version of the device is available as

Contextual Info: AmPAL*10H20EV8/AmPALI0020EV8 IMOX-III E C L Program m able Array Logic PR ELIM IN A RY Asynchronous-RESET and PRESET capability Power-up RESET capability PRELOAD for improved testability Special designed-in test features for AC and DC testing Platinum-silicide fuses ensure high programming yield,

Xilinx XC2S150E

Abstract: AMD flash xilinx so20 XC17S
Contextual Info: XC18V512 512Kb Y Y Y 3.3V Y Y XC18V01 1Mb Y Y Y 3.3V Y Y XC18V02 2Mb Y Y 3.3V Y Y XC18V04 4Mb Y Y 3.3V Y Y Y Y Y Y Y Y Y 3.3V Y Y XC17V04 4Mb Y Y Y 3.3V Y Y 3.3V I/O Voltage 2.5V VQ44 Y PC20 Y Y 3.3V Y SO20 Y 3.3V Y Y VO8 Y 16Mb PD8 8Mb XC17V16 FPGA XC17V08

XC2S100E

Contextual Info: XC18V512 512Kb Y Y Y 3.3V Y Y XC18V01 1Mb Y Y Y 3.3V Y Y XC18V02 2Mb Y Y 3.3V Y Y XC18V04 4Mb Y Y 3.3V Y Y Y Y Y Y Y Y Y 3.3V Y Y XC17V04 4Mb Y Y Y 3.3V Y Y 3.3V I/O Voltage 2.5V VQ44 Y PC20 Y Y 3.3V Y SO20 Y 3.3V Y Y VO8 Y 16Mb PD8 8Mb XC17V16 FPGA XC17V08

Contextual Info: AmPAL*10H20EV8/AmPAL10020EV8 IMOX-III ECL Programmable Array Logic PRELIMINARY Asynchronous-RESET and PRESET capability Power-up RESET capability PRELOAD for improved testability Special designed-in test features for full AC and DC testing Platinum-silicide fuses ensure high programming yield,

amd 2901 alu

Abstract: amd 2901 pinout diagram amd 2901 amd 2901 core 4 bit microprocessor using vhdl "Dual-Port RAM" basic microprocessor block diagram AM2901 C2901 8 BIT ALU using vhdl
Contextual Info: ac_cast_c_2901.fm Page 1 Thursday, October 8, 1998 10:52 AM C2901 Microprocessor Slice October 12, 1998 Product Specification AllianceCORE Facts CAST, Inc. 24 White Birch Drive Pomona, New York 10907 USA Phone: +1 914-354-4945 Fax: +1 914-354-0325 E-Mail: info@cast-inc.com

amd 2901 alu

Abstract: 8 BIT ALU design with verilog 8 BIT ALU using vhdl amd 2901 pinout diagram 32 BIT ALU design with vhdl amd 2901 verilog 4 bit microprocessor using vhdl 32 bit alu using vhdl 32 bit ALU vhdl am 2901 verilog
Contextual Info: C2901 Microprocessor Slice June 26, 2000 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Core documentation Design File Formats EDIF Netlist; .ngc VHDL/Verilog Source RTL available extra Constraints File