ALVC126 Search Results

msi 7267 MOTHERBOARD SERVICE MANUAL

Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Contextual Info: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

ALVC126

Abstract: IDT74ALVC126
Contextual Info: ALVC126 3.3V CMOS QUADRUPLE BUS BUFFER GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS ALVC126 ADVANCE INFORMATION DESCRIPTION: FEATURES: – – 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS ALVC126 ADVANCE INFORMATION DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSOP and

A115-A

Abstract: SN74ALVC126 SN74ALVC126D SN74ALVC126DR SN74ALVC126NSR
Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111F – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)

Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

ALVC126

Abstract: IDT74ALVC126
Contextual Info: ALVC126 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS ALVC126 FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

va126

Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS DESCRIPTION: FEATURES: - ALVC126 ADVANCE INFORMATION 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1.27mm pitch SOIC, 0.65mm pitch SSOP and

SN74ALVC126

Abstract: SN74ALVC126D A115-A C101
Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

A115-A

Abstract: C101 SN74ALVC126 SN74ALVC126D va126
Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com • • • • • SCES111I – JULY 1997 – REVISED JUNE 2004 Operates From 1.65-V to 3.6-V VCC Max tpd of 3.1 ns at 3.3-V VCC ±24-mA Output Drive at 3.3-V VCC Latch-Up Performance Exceeds 250 mA Per

VA126

Abstract: A115-A SN74ALVC126 SN74ALVC126D SN74ALVC126DR SN74ALVC126NSR
Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111F – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)

A115-A

Abstract: C101 SN74ALVC126 SN74ALVC126D
Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

ALVC126

Abstract: IDT74ALVC126
Contextual Info: ALVC126 3.3V CMOS QUADRUPLE BUS BUFFER GATE INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS DESCRIPTION: FEATURES: – – – – – – – – ALVC126 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3ĆSTATE OUTPUTS SCES111G − JULY 1997 − REVISED AUGUST 2003 D D D D D D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

A115-A

Abstract: C101 SN74ALVC126 SN74ALVC126D VA126
Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages Extended commercial range of - 40° C to +85° C

Contextual Info: ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

g5d2

Abstract: ths730a PM10-24S05 backplane layout SN74GTLPH1655 LT1083
Contextual Info: GTLP Evaluation Module EVM User’s Guide June 2001 Standard Linear & Logic Printed in U.S.A. 0601 SCEA023 GTLP Evaluation Module (EVM) User’s Guide SCEA023 June 2001 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products