ALVC125 Search Results

A115-A

Abstract: SN74ALVC125 SN74ALVC125D SN74ALVC125DR SN74ALVC125NSR VA125
Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110E – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)

va125

Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

ALVC125

Abstract: IDT74ALVC125
Contextual Info: ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS DESCRIPTION: FEATURES: – – – – – – – – ALVC125 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS ALVC125 FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

S0141

Contextual Info: 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS DESCRIPTION: FEATURES: - ALVC125 ADVANCE INFORMATION 0.5 MICRON C M O S T echnology ESD > 2000V per M IL-STD -883, M ethod 3015; > 200V using m achine m odel C = 200pF, R = 0 1.27mm pitch SOIC, 0.65m m pitch SSO P and

ALVC125

Abstract: IDT74ALVC125
Contextual Info: ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS ALVC125 FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

IDT74ALVC125

Abstract: ALVC125
Contextual Info: ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS DESCRIPTION: FEATURES: – – – – – – – – – ALVC125 ADVANCE INFORMATION 0.5 MICRON CMOS Technology

ALVC125

Abstract: IDT74ALVC125
Contextual Info: ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS ALVC125 ADVANCE INFORMATION DESCRIPTION: FEATURES: – – 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages Extended commercial range of - 40° C to +85° C

Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

A115-A

Abstract: C101 SN74ALVC125 SN74ALVC125D VA125 VA-125
Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

A115-A

Abstract: C101 SN74ALVC125 SN74ALVC125D VA-125
Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3ĆSTATE OUTPUTS SCES110F − JULY 1997 − REVISED AUGUST 2003 D D D D D D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

C101

Abstract: SN74ALVC125 SN74ALVC125D A115-A
Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

ENG-46158

Abstract: TMS320TCI6484 SCEA035 scas683 TMS320C6457 DSP Ethernet Media Access Controller mdio level translator slls781 SPRU732 jesd79-2B CDCL1810
Contextual Info: Application Report SPRAAV7B—October 2009 TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide High-Performance and Multicore Processors Randy Rosales Abstract This application note describes hardware system design considerations for the TMS320TCI6484 and TMS320C6457 DSPs.

SN74ALVC125NSR

Abstract: A115-A SN74ALVC125 SN74ALVC125D SN74ALVC125DR
Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110E – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)

Contextual Info: 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS ALVC125 ADVANCE INFORMATION DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSOP and

A115-A

Abstract: C101 SN74ALVC125 SN74ALVC125D
Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

ENG-46158

Abstract: TMS320TCI6487 TCI6487 scas683 SN65LVS108 C6000 CDCL6010 DDR2-400 SPRU811 jesd79-2B
Contextual Info: Application Report SPRAAG5D – December 2006 – Revised November 2009 TMS320TCI6487/88 Hardware Design Guide Ronald Lerner .

ENG-46158

Abstract: TMS320C6474 TMS320TCI6487 C6000 C6474 CDCL6010 DDR2-400 DDR2-667 SPRU811 sprue
Contextual Info: Application Report SPRAAW7A – August 2008 – Revised November 2009 TMS320C6474 Hardware Design Guide Ronald Lerner . ABSTRACT

Contextual Info: ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V