ALTERA EPM 7064 Search Results

EPM7064 100-Pin Package Pin-Out Diagram

Abstract: EPM7064 altera epm 7064 EPM7064-12 EPM7064-15 7064
Contextual Info: EPM 7064 EPLD Features □ Preliminary Information □ □ □ □ High-performance, erasable CM OS EPLD based on second-generation MAX architecture 1,250 usable gates Combinatorial speeds with tPD = 7.5 ns Counter frequencies up to 125 MHz Advanced 0.8-m icron CM OS EEPROM technology

altera jed to pof convert

Abstract: EP1810 jedec EPM memory epx780 ep330
Contextual Info: / a \| l l l" £ Glossary March 1995 A Altera Hardware Description Language AHDL A ltera's design entry language. AH DL is com pletely integrated into M A X +P L U S II, and allows the designer to enter and edit Text Design Files (.tdf) with the M A X +PLU S II Text

Contextual Info: M A X 7000A Includes M A X 7000AE Programmable Logic Device Family September 1999. ver. 2. Data Sheet • F e a tu r e s . ■ P re lim in a ry Inform atio n ■ ■ ■ ■ ■ H igh-perform ance CM OS EEPRO M -based program m able logic devices PLDs built on second-generation M ultiple A rray MatriX

K1336

Abstract: vhdl code for turbo 10H119
Contextual Info: M U M M A X 7000A Includes M A X 7000AE Programmable Logic Device Family June 1999, ver. 2. • F e a tu r e s . ■ P re lim in a ry Inform atio n ■ ■ ■ ■ ■ H igh-perform ance CM OS EEPRO M -based program m able logic devices PLDs built on second-generation M ultiple A rray MatriX

7256S

Abstract: MPU 6000 7160E ATIC 164 D2
Contextual Info: «/SToSSIs MAX 7000 MAX 7000S Programmable Logic Device Family May 1999. ver. 6 Datasheet Features • ■ ■ ■ ■ ■ m High-perform ance, EEPRO M -based program m able logic devices PLDs based on second-generation M ultiple A rray M atrix (MAX®)

epm7064 adapter

Abstract: EPM71925 MAX7000E epm7192 EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E
Contextual Info: ¿ s u t* M A X 7000 MAX 7000S Programmable Logic Device Family July 1999. ver. 6.01 Datasheet Features • ■ ■ ■ ■ ■ _ High-performance, EEPROM-based programmable logic devices PLDs based on second-generation Multiple Array MatriX (MAX®)

EPM7064 100-Pin Package Pin-Out Diagram

Contextual Info: EPM 7064 EPLD Features □ Preliminary □ □ □ Information □ □ High-performance, erasable CM OS EPLD based on second-generation M ultiple Array M atrix MAX architecture 1,200 usable gates Com binatorial speeds w ith tPD = 10 ns Clock frequencies up to 100 MHz

PJO 399

Abstract: PJO 389 PJO 499 B13128 pjo 489 7512A PJO 376 PJO 386
Contextual Info: MMMA. MAX 7000A Includes MAX7000AE Programmable Logic Device Family May 1999, ver. 2 Data Sheet Features. • ■ ■ Prelim inary Information ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

7064B

Abstract: m7512b
Contextual Info: MAX 7000B M Ï Ï I 3 Â. Programmable Logic Device Family August 1999. ve Data Sheet Features. • Preliminary Information ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array M atrix (MAX ) architecture (see Table 1)

em 495 b12

Contextual Info: MAX 7000A Includes MAX 7000AE Programmable Logic Device Family May 1999» ver.2 Data Sheet Features. H igh-perform ance CM O S EEPRO M -based program m able logic devices PLDs built on second-generation M ultiple Array M atriX (MAX ) architecture (see Table 1)

Contextual Info: MAX 7000 Includes MAX 7000E & MAX 7000S Programmable Logic Device Family January 1998. ver. 5 Features. Data Sheet • ■ ■ ■ ■ ■ ■ High-perform ance, EEPR O M -based program m able logic devices P L D s based on second-generation M u ltip le A rra y M a triX (M A X )

ATIC 164 D2 48 pin

Abstract: EPM7000AE MAX-7Q 0
Contextual Info: MAX 7000A Includes MAX 7000AE Programmable Logic Device Family October 1998, ver, 1,2 Data Sheet Features. Form erly know n as M ichelangelo devices H igh-perform ance CM O S EEPRO M -based program m able logic devices PLDs built on second-generation M ultiple Array M atriX

K4113

Abstract: L9170 C520B K4097 L4887 A844C k3113
Contextual Info: M AX 7000A Includes M A X 7000AE Programmable Logic Device Family January 1999. ver. 1.3 Data Sheet Form erly know n as M ichelangelo devices High-performance CM OS EEPROM -based program m able logic devices PLDs built on second-generation M ultiple Array MatriX

73d12

Abstract: epm7032 algorithm
Contextual Info: Includes MAX 7000E & MAX 7000S M A X 7000 Programmable Logic Device Family May 1999. ver. 6 Data Sheet Featll res • ■ ■ ■ ■ ■ H igh-perform ance, EEPROM -based p rogram m able logic devices PLDs based on second-generation M ultiple A rray M a trix (MAX®)

208 pin rqfp drawing

Abstract: 240 pin rqfp drawing ALTERA flex 81188 altera 5032 8636a EPF81188AGC232-3 100 PIN "PGA" ALTERA DIMENSION 5130a PL-SKT/Q160 Altera EPC
Contextual Info: y /^ \ [^ V a \ Ordering Information M a rc h 19 95, ver. 7 Altera DBViC6S Figure 1 explains the ordering codes for Altera devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. Some codes use relative numbers e.g., -1, -2 to designate

Contextual Info: Includes MAX 70 0 0 E & MAX 7000S M A X 7000 Programmable Logic Device Family February 1998. ver. 5.01 Features Data Sheet • ■ ■ ■ ■ ■ ■ High-performance, EEPROM-basedprogrammable logic devices PLDs based on second-generation Multiple Array Matrix (MAX)

max 7128S programmer

Abstract: 7128E 10K30 EPF81188AGC232-3 ep600i altera 5032 PLSKT 10K20 epm9320 7160E
Contextual Info: Ordering Information June 1996, ver. 8 Altera Devices Figure 1 explains the ordering codes for Altera devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. Some codes use relative numbers e.g., -1, -2 to designate

PLE3-12 EP1810

Contextual Info: ÆoniM Glossary June 1996 A Altera Hardware Description Language AHDL A ltera's design entry language. AHDL is a highlevel, modular language that is com pletely integrated into M A X +P L U SII. You can create AHDL Text Design Files (.tdf) with the M A X+PLUS II Text Editor or any standard text

7032AE

Abstract: 9560a Altera 7032 3128A 7256E 10K100A 7032B programmer EPLD 10K50 PL-ASAP
Contextual Info: Ordering Information March 2001, ver. 10 Altera Devices Altera Corporation A-GN-ORD-10 Figure 1 explains the ordering codes for Altera® devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. Some codes use relative numbers e.g., -1, -2 to

K 7256 M

Abstract: max 7128S programmer PL-SKT/Q160
Contextual Info: Ordering Information June 1996, ver. 8 Altera Devices Figure 1 explains the ordering codes for Altera devices. Devices that have m ultiple pin counts for the same package include the pin count in their ordering codes. Som e codes use relative numbers e.g., -I, -2 to designate

Contextual Info: M A X 7000A Programmable Logic Device Family February 1998. ver. 1.01 Data Sheet Formerly known as Michelangelo devices High-performance CMOS EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array Matrix (MAX ) architecture (see Table 1)

Altera flex 8k PCi

Abstract: 10K50 10K30A altera epc 610 ALTERA MAX 5000 programming plcc 20pin socket EPM7032L 9560a flex 10k20 7160S
Contextual Info: Ordering Information January 1998, ver. 9 Altera Devices Figure 1 explains the ordering codes for Altera devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. Some codes use relative numbers e.g., -1, -2 to designate

Contextual Info: M AX 7000A Includes MAX 7000AE Programmable Logic Device Family June 1998. ver. 1.10 Data Sheet Features. F orm erly k n o w n as M ichelangelo devices H igh-perform ance CMOS EEPROM -based pro g ram m ab le logic devices PLDs b u ilt o n second-generation M ultiple A rray M atriX

alien h3

Abstract: epm7192s pin
Contextual Info: includes MAX 7000E& MAX 700OS M AX 7000 Programmable Logic Device Family July ^898, ver. 5.03 Features . . . S8 88 £8 S8 SSS H igh-perform ance, EEPROM -based p rogram m able logic devices PLDs based on second-generation M ultiple A rray MatriX (MAX)