ALOA Search Results

74561

Contextual Info: — 74561 — Synchronous Presettable Binary Counter 3-State Vcc RCO CCO G Qa Qb J T oI X h U T i U T T I J u U i ^ Qc Qo ENT SLOAD ^ m i ' n i n » n * r i ! n « n i n » -I» i i « r ALOAD CLK A B C D ENP ACIR SCLR GND o c? — k , ? n r i m o 5 6 9 <r> U / D

74560 counter

Abstract: 74560 bc 568 ad 561 d
Contextual Info: - 252- 74560 Synchronous Presentable Deca'de Counter 3-State Vcc RCO CCO G Q* Qe Qc Qd ENT SLOAD JT o lJT iU T IU T T U if U ^ i n i M o h i M y i i i h i i H i h i M i n i r * ALOAD CLK o o - k, A B C D EN P ACLR SCLR GND ? ij ») o 568 <n U / D % # Is] m □ - K \z % t z _ t z m

JAN 1N4248

Abstract: 1N4245 1N4247 1N4248 1N4249
Contextual Info: X iÚ JiS . . Microsemi Corp. 1N4245 thru 1N4249 T.hp aloae expens SANTA A N A , CA F o r m ore in fo rm a tio n cali: 714 979-8220 MILITARY RECTIFIERS FEATURES • M ICRO M INIATURE PACKAGE • VO IDLESS HERMETICALLY SEALED G LA SS PACKAGE • TRIPLE LAYER PASSIVATION

Contextual Info: SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995 • description These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading.

Contextual Info: External Memory Interfaces in Stratix V Devices 7 2012.12.28 SV51008 Subscribe Feedback The Stratix V devices provide an efficient architecture that allows you to fit wide external memory interfaces to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are

18PIN

Abstract: HE8P1702AP HE8P1702AS
Contextual Info: HE8P1702A HE8P1702A SERIES TARGET SPECIFICATION 1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

P17W

Abstract: RESONATOR 4MHZ HE8P1604K HE8P1604S P13W
Contextual Info: HE8P1604 HE8P1604 PRODUCT SPECIFICATION 1. GENERAL DESCRIPTION . 3 2. FEATURES . 3

Contextual Info: AMPLIFIER UNIT C7319 The C7319 which furnishes current-to-voltage conversion circuit is designed for use with current sources like photomultiplier tubes. The C7319 has three switchable conversion ratios; 0.1, 1 and 10 V/µA and also has two switchable bandwidth selections.

smd transistor 43t

Abstract: on line ups circuit schematic diagram capacitor 103 .01uf SMPTE274 2d2 smd transistor THS8134 AMP 103309-1 1080i field pattern black EPM7128SLC84-7 SMD G8
Contextual Info: THS8133/34 EVM User’s Guide September 1999 Mixed Signal Products SLVU020A IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

Contextual Info: LTC1660 L iim TECHNOLOGY M icropow er O ctal 10-Bit DAC FEATURES DESCFHFTIOn • 8 DACs in the Board Space of an SO-8 ■ 2.7V to 5.5V Single Supply Operation ■ ICC TYP = 450|oA, Just 56|aA per DAC ■ 1|oA Sleep Mode for Extended Battery Life ■ Restores Last DAC Setting After Sleep

NEC VFD Display FIP13

Abstract: sony tuners NEC fip4 FIP16 nec fip20 NEC VFD fip11 NEC VFD FIP9 uPD780226 uPD780228 uPD78044H
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

difference between intel 8086 and intel 80186 pro

Abstract: 82C08 intel 82c08 difference between intel 80186 and intel 80286 pro 82C08-8 80188 programming 82C08-10 intel 80186 pin out IC 8208 intel 8208
Contextual Info: in te i. 82C08 CHMOS DYNAMIC RAM CONTROLLER • ■ 0 Walt State with INTEL ^Processors iAPX 286 1 10, 8 MHz J iAPX 186/88 1 86/88 J 82C08-20 20 MHz 82C08-16 16 MHz 82C08-10 10 MHz 82C08-8 8 MHz ■ Supports 64K and 256K DRAMs (256K x 1 and 256K x 4 Organizations)

Broken Conductor Detection for Overhead Line Distribution System

Abstract: verilog code for CORDIC to generate sine wave verilog code for cordic algorithm for wireless la TXC 13.56 sma diode h5c intel 945 motherboard schematic diagram 2005Z fet k241 EARTH LEAKAGE RELAY diagram schematic diagram for panasonic inverter air cond
Contextual Info: Stratix GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SGX5V1-1.2 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

circuit diagram of 8-1 multiplexer design logic

Abstract: vhdl code for complex multiplication and addition ieee floating point multiplier vhdl vhdl projects abstract and coding verilog code for floating point adder altera cyclone 3 digital clock verilog code digital clock vhdl code free vhdl code download for pll ieee floating point vhdl
Contextual Info: Section III. Synthesis As programmable logic devices become more complex and require increased performance, advanced design synthesis has become an important part of the design flow. In the Quartus II software you can use the integrated Analysis and Synthesis

alt_iobuf

Abstract: ep3*SL150F1152C2 altera double data rate megafunction sdc UG-01032-4
Contextual Info: ALTDLL and ALTDQ_DQS Megafunctions User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 9.1 4.0 May 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

logic diagram to setup adder and subtractor

Abstract: EP1C12
Contextual Info: 2. Cyclone Architecture C51002-1.6 Functional Description Cyclone devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and

add round key for aes algorithm

Abstract: detail of half adder ic DIN 5463 2-bit half adder handbook texas instruments IC to design 2 by 2 binary multiplier SE 135 pin configuration verilog code for twiddle factor ROM transistor c789 6A ep3sl1501152
Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.1 July 2010 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Contextual Info: H Y 5 1 V 16 4 1 O A S e r ie s “HYUNDAI 4M X 4-bit CMOS DRAM with WPB PRELIMINARY DESCRIPTION The HY51V16410A is the new generation and fast dynamic RAM organized 4,194,304 x 4-bit. The HY51V16410A utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide

MW20M

Contextual Info: REV. PART 59 NU MB ER LED LE D CO L OR -2001-107 59 - 2 0 0 1 - 1 13 59 -2101-102 59 -2101-107 59 - 2 I 0 I - I 13 H I .E F F . RED LUMINOUS -2201-102 59 -2201-107 59 - 2 2 0 1 - 1 13 59 -2301-102 59 -2301-107 HI .E FF .R ED OREEN AT AIGaaS TYP MAX 5.6 9.8

EP1C6 equivalent

Abstract: 100 PIN tQFP ALTERA DIMENSION c 5929 hot MA-2395 ps1784
Contextual Info: Cyclone FPGA Family March 2003, ver. 1.1 Introduction Preliminary Information Features. Data Sheet The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic elements LEs and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Q204B

Abstract: DM-4101L DM-4102 B141s DM-4200 115VAC-to-5V
Contextual Info: D M -4 2 0 0 4 1/2 Digit D ifferen tial LED DPM w ith Data Outputs PRODUCT DATA AND USER'S GUIDE FEATURES • Low Cost 4 Va Digit DPM with LED Display • Balanced Differential Inputs • Digit Serial BCD Outputs — Can Drive Remote Slave Display DM-4102

EP1S60

Abstract: "Single-Port RAM"
Contextual Info: Chapter 1. Introduction S51001-3.1 Introduction The Stratix family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities of up to 79,040 logic elements LEs and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal

diode jd 4.7-16

Abstract: MA4001
Contextual Info: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-1.2 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

bi directional dc motor speed controller

Abstract: PS2 Series connector SN8P22 SONiX Technology Company 731 zener diode circuit diagram for joystick to USB IC 8 PIN 2267 usb/PWM IC 8 PIN 2267 zener diode B3 LQFP48
Contextual Info: SN8P2260 Series USB 2.0 Low-Speed 8-Bit Micro-Controller SN8P2260 Series USER’S MANUAL SN8P2267 SONiX 8-Bit Micro-Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not