M40Z300
Abstract: M48Z128 M48Z128V M48Z128Y SOH28
Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES
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m48z128m48z128ym48z128vm40z300+1soh28
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M48Z128
Abstract: M48Z128Y SOH28 TSOP32
Contextual Info: M48Z128 M48Z128Y 1 Mbit 128Kb x8 ZEROPOWER SRAM • INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS of DATA RETENTION in the ABSENCE of POWER ■ AUTOMATIC POWER-FAIL CHIP DESELECT
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m48z128m48z128y128kbpmdip32+428-pin32-leadsoh28tsop32
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Contextual Info: M48Z128 M48Z128Y 5.0 V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of
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M48Z128
Abstract: M48Z128V M48Z128Y SOH28 TSOP32
Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE
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m48z128m48z128ym48z128v32-pin+2soh28tsop32
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M48Z128
Abstract: M48Z128Y
Contextual Info: M48Z128 M48Z128Y 1 Mbit 128Kb x8 ZEROPOWER SRAM INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER AUTOMATIC POWER-FAIL CHIP DESELECT
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m48z128m48z128y128kbm48z128/128y |
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SOH28
Abstract: TSOP32 M48Z128 M48Z128V M48Z128Y
Contextual Info: M48Z128 M48Z128Y, M48Z128V 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE
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m48z128m48z128ym48z128v28-pin+332leadsoh28tsop32
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Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE
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m48z128m48z128ym48z128v32-pin+228-pin32-lead
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M40Z300
Abstract: M48Z128 M48Z128V M48Z128Y D 4242 CP1621
Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES
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m48z128m48z128ym48z128vm40z300+2d 4242cp1621
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M48Z128V
Abstract: M48Z128Y SOH28 TSOP32 M48Z128 M68Z128
Contextual Info: M48Z128 M48Z128Y, M48Z128V 1 Mbit 128Kb x8 ZEROPOWER SRAM • INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS of DATA RETENTION in the ABSENCE of POWER ■ AUTOMATIC POWER-FAIL CHIP DESELECT
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m48z128m48z128ym48z128v128kb+5pmdip3228-pinsoh28tsop32m68z128
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Contextual Info: M48Z128 M48Z128Y 5.0 V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of
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m48z128m48z128y |
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Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE
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m48z128m48z128ym48z128v28-pin+132-leadd
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AI02169
Abstract: M48Z128 M48Z128Y AI01196
Contextual Info: M48Z128 M48Z128Y 1Mb 128K x 8 ZEROPOWER SRAM INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION
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m48z128m48z128ym48z128/128yai02169+1ai01196
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M48Z128
Abstract: M48Z128V M48Z128Y M40Z300
Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE
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m48z128m48z128ym48z128v32-pin+1m40z300
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M48Z128
Abstract: M48Z128V M48Z128Y AN1012
Contextual Info: M48Z128 M48Z128Y, M48Z128V 5.0 V or 3.3 V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of
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m48z128m48z128ym48z128vpmdip32+1an1012
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