AHB TO I2C Search Results

Contextual Info: Freescale Semiconductor Technical Data MSC7116 Rev. 7, 10/2005 MSC7116 DMA 32 ch Trace Buffer (8 KB) ASEMI DSP Extended Core 64 AHB-Lite Crossbar Switch OCE SC1400 Core 64 to IPBus Fetch Unit Instruction Cache (16 KB) Extended Core Interface 128 M2 SRAM

GPID-7

Abstract: GPIA10 duplex thermocouple C10C8 pcb MC711 GPIA21
Contextual Info: Freescale Semiconductor Technical Data MSC7116 Rev. 8, 12/2005 MSC7116 DMA 32 ch Trace Buffer (8 KB) ASEMI DSP Extended Core 64 AHB-Lite Crossbar Switch OCE SC1400 Core 64 to IPBus Fetch Unit Instruction Cache (16 KB) Extended Core Interface 128 M2 SRAM

Contextual Info: Freescale Semiconductor Technical Data MSC7116 Rev. 6, 4/2005 MSC7116 DMA 32 ch Trace Buffer (8 KB) ASEMI DSP Extended Core 64 AHB-Lite Crossbar Switch OCE SC1400 Core 64 to IPBus Fetch Unit Instruction Cache (16 KB) Extended Core Interface 128 M2 SRAM 64

verilog code for i2c

Abstract: ahb to i2c verilog code verilog code for I2C MASTER verilog code for I2C MASTER slave i2c master verilog code atmel 8051 i2c sample code ahb to i2c design implementation 8051 I2C PROTOCOL 89C51IC2 verilog code for amba ahb master
Contextual Info: I2C-HS Master/Slave Bus Controller Core The I2C-HS core implements a serial interface that meets the Philips I2C Bus specification version 2.1. It is compliant with the PVCI Peripheral Virtual Component Interface standard which is an open standard for SoC On-Chip Bus.

89C51IC2

Abstract: 8051 THROUGH I2C PROTOCOL EP3SE50 ahb to i2c design implementation
Contextual Info: I2C-HS Master/Slave Bus Controller Megafunction The I2C-HS megafunction implements a serial interface that meets the Philips I2C Bus specification version 2.1. It is compliant with the PVCI Peripheral Virtual Component Interface standard which is an open standard for SoC On-Chip Bus.

3S100E-5

Abstract: 8051 THROUGH I2C PROTOCOL ahb to i2c design implementation 89C51IC2 "programmable clock" i2c texas ahb to i2c testbench of a transmitter in verilog
Contextual Info: I2C-HS Master/Slave Bus Controller Core The I2C-HS core implements a serial interface that meets the Philips I2C Bus specification version 2.1. It is compliant with the PVCI Peripheral Virtual Component Interface standard which is an open standard for SoC On-Chip Bus.

APB to I2C interface

Abstract: spi controller with apb interface AMBA AHB DMA vhdl code for ddr sdram controller with AHB interface AMBA APB spi Cypress FX2 design of dma controller using vhdl ITU656 ahb to i2c SIMPLE VGA GRAPHIC CONTROLLER
Contextual Info: LCD-Pro IP LCD-Pro IP modules DS0031 v1.01 – 20 July 2009 Datasheet: Table 1: Core Facts Implementation data Documentation Datasheet, User’s Manual Design File Formats EDIF netlist Constraint Files LPF file Reference Designs & Implementation examples

atmel h020

Abstract: atmel 0713 ATMEL 620 spear linux uart baud rate spear AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022
Contextual Info: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates

atmel h020

Abstract: atmel 0713 AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 usb 3 sm Flash drive controller M25Pxxx state machine for ahb to apb bridge
Contextual Info: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates

ph6n

Abstract: transistor PH6n SPEAR-09-P022 TA 8268 analog ta 8268 transistor ph0n p022 UART TTL buffer ARM926EJ-S electrical characteristic PH5N
Contextual Info: SPEAR-09-P022 SPEAr Plus600 dual processor cores Preliminary Data Features • Dual ARM926EJ-S core @333MHz. ■ 600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool.

H122

Abstract: ph6n PH5N ph8n transistor PH6n ph7n ph4n ARMv5TEJ 0xE12 E31821
Contextual Info: SPEAR-09-H122 SPEAr Head600 Preliminary Data Features • ARM926EJ-S core @333MHz. ■ 600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool. ■ Multilayer AMBA 2.0 compliant Bus with fMAX

lqfp64

Abstract: LQFP64 package ARM7 LPC2138 LQFP-64 ARM7TDMI-S pll nxp lpc2138 32 KB SRAM 16C550 LPC2131 LPC2132
Contextual Info: 60-MHz, 32-bit microcontroller with ARM7TDMI-S core LPC213x ARM7-based microcontrollers with two 10-bit ADCs and 10-bit DAC These powerful yet cost-effective microcontrollers have up to 512 KB of ISP/IAP Flash and up to 32 KB of SRAM. Each has up to two 10-bit A/D converters, a 10-bit D/A converter, two I2C-bus

80C552

Contextual Info: Uses two wires to transfer information between devices o Serial Clock Line SCL SCL I2CS Slave Bus Controller Megafunction The I2CS Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all slave transfer modes to and from the I2C bus. The I2CS

TSMC 0.18Um

Abstract: TSMC 0.13um process specification 80C552 TSMC 90nm
Contextual Info: Uses two wires to transfer information between devices o Serial Clock Line SCL SCL I2CS Slave Bus Controller Core The I2CS Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all slave transfer modes to and from the I2C bus. The I2CS

tag a2

Abstract: ARGB888 CY7C68013A ITU656 RGB565 RGB888 ECP2-50 RGB-16 802.3 CRC32
Contextual Info: LCD-Pro IP user manual UM0011 v1.0 – 14 July 2009 User Manual: Overview This document describes the LCD-Pro IP architecture, including the next cores: UltiEVC display controller, UltiEBB 2D graphic accelerator, UltiEMC DDR memory controller, UltiVidin video input core, UltiDMA DMA controller, UltiSPI2AHB SPI

LPC2300

Abstract: VICvectCntl0-15 ARM7TDMI-S bsdl vic lpc2378 LPC2400 AN10576 LPC2378 8084 microcontroller arm7 bsdl LPC2378 Timer application notes
Contextual Info: AN10576 Migrating to the LPC2300/2400 family Rev. 01 — 1 February 2007 Application note Document information Info Content Keywords LPC2000, LPC23xx, LPC24xx, Migration Abstract This application note covers the important features that were added to the LPC23xx/24xx family of devices. These features should be considered if

Contextual Info: SPEAR-09-H022 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC DATA BRIEF Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates 16K LUT equivalent with 8 channels internal

LPC24XX

Abstract: timer video tms 9937 LPC2478FBD208 mst 702 lf LPC2468 pcb LPC2478 ARM7TDMI motor driver ic 7324 LPC247x LPC2478 pcb LPC2468FBD208
Contextual Info: UM10237 LPC24XX User manual Rev. 04 — 26 August 2009 User manual Document information Info Content Keywords LPC2400, LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, LPC2478, ARM, ARM7, 32-bit, Single-chip, External memory interface, USB 2.0, Device, Host, OTG, Ethernet, CAN, I2S, I2C, SPI, UART, PWM, IRC,

M2S050-1FG484I

Abstract: M2s010-fgg484 axi interface ddr3 memory controller M2S050-FG484 M2S050T-1FG484I M2S120T-1FC1152I SECDED M2S005-VF400 M2S010T-FGG484 M2S050T-FG896
Contextual Info: Product Brief SmartFusion2 System-on-Chip FPGAs Microsemi’s SmartFusion 2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM® Cortex -M3 processor, and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most

Contextual Info: STA2062 Cartesio family Infotainment application processor with embedded GPS Data Brief Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High performance ARM926 MCU up to 333 MHz MCU memory organization – Cache: 16 KByte instruction, 16 KByte data

Contextual Info: SPEAR-09-H020 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC DATA BRIEF Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates with 8 channels internal DMA high speed

installation diagram of ip camera

Abstract: 7 inch 800x480 LCD panel touch lcd digital 7 inch TFT LCD WVGA QVGA GRAPHICS LCD DISPLAY rgb led video colour display ITU656 M25P32 BLOCK DIAGRAM OF 4 wire resistive TOUCH panel implementation of eeprom interfacing with i2c
Contextual Info: L A T T I C E E V A L U A T I O N K I T LCD-Pro Evaluation Kit Advanced Touch-Screen Video Graphics Controller The LCD-Pro Evaluation Kit enables evaluation of the LCD-Pro library, a set of flexible, configurable IP cores which can be used to implement versatile and powerful display

INS16Cx50

Abstract: cea f23 rtc 1301 cea g22 matrix m21 ARM926EJ-S LPC3180 LPC3180FEL320 PL080 difference between arm7 and arm9
Contextual Info: LPC3180 16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface Rev. 01 — 2 June 2006 Preliminary data sheet 1. General description The LPC3180 is an ARM9-based microcontroller for embedded applications requiring

STA2062

Abstract: STa2062 ARM926 LFBGA361 cartesio LFBGA36 ST OTG controller vic-16 ARM926 ARM926EJ ARM processor .4mm pitch
Contextual Info: STA2062 Cartesio Infotainment application processor with embedded GPS Data Brief Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High performance ARM926 MCU up to 333MHz MCU memory organization – Cache: 16KByte instruction, 16KByte data