AGERE FPP Search Results

tag 8833

Abstract: RSP RELAY scr tag 89 marking RSP tag b1
Contextual Info: Product Brief June 2001 PayloadPlus Agere System Interface Introduction Agere System Interface The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full

tag 8833

Abstract: RSP RELAY scr tag 89 marking RSP asi bus MASTER BUS asi
Contextual Info: Preliminary Product Brief April 2000 NPASI PayloadPlus Agere System Interface Introduction Agere System Interface The Lucent PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full programmability.

Transistor KU 607 VC

Abstract: OC-40 a bus system with two 7495
Contextual Info: Product Brief April 2001 PayloadPlus Voice Packet Processor Introduction • The Voice Packet Processor VPP is part of the Agere Systems PayloadPlus family of network processors. The VPP is designed to fit on the data path between the Fast Pattern Processor (FPP)

Agere RSP

Abstract: Agere ASI OC-40
Contextual Info: Product Brief April 2001 Voice Packet Processor Introduction • The Voice Packet Processor VPP is part of the Agere Systems PayloadPlus family of network processors. The VPP is designed to fit on the data path between the Fast Pattern Processor (FPP)

Agere ASI

Abstract: Agere FPP
Contextual Info: Product Brief April 2001 PayloadPlus Fast Pattern Processor Introduction Fast Pattern Processor The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full

scheduling

Abstract: Agere ASI POS-PHY utopia
Contextual Info: Product Brief April 2001 PayloadPlus Routing Switch Processor Introduction The Routing Switch Processor The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full

Agere ASI

Abstract: a bus system with two 7495 "routing tables"
Contextual Info: Product Brief November 2001 PayloadPlus Fast Pattern Processor Introduction Fast Pattern Processor The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full

Agere FPP

Abstract: C language to count 0-9
Contextual Info: The Case for a Classification Language Eric J. Rothfus • Agere, Inc. Abstract This paper details the need for a high-level “Classification Language” in communications. It first describes classification and its relationship and role within communications. Necessary attributes

Agere ASI

Abstract: APP550 NP10 TM10 "L2TP"
Contextual Info: Product Brief Brief Product September 2002 September 2002 Advanced PayloadPlus Network Processor APP550 Introduction The Agere Systems Advanced PayloadPlus Network Processor device is the latest addition to the PayloadPlus family of products. It offers a

agere VPP

Abstract: data sheet ic 7495 gvrp 7495 ic data sheet MPC750 tornado "Spanning Tree" "OSPF" 8021G
Contextual Info: Product Brief June 2001 Tornado Managed Systems and PayloadPlus Introduction The growth of the Internet brings constant challenges to vendors who supply data networking infrastructure equipment, and to manufacturers, who are expected to provide increasingly higher performance, lower cost

LG1627BXC

Abstract: TADM042G5 TDAT042G5 TRCV012G5 TTRN012G5 IXF1002 IXF440 transmit data through ethernet to fpga by vhdl
Contextual Info: Product Brief June 2001 Gigabit Ethernet/Fast Ethernet POS-PHY Bridge Overview The gigabit Ethernet GbE /fast Ethernet POS-PHY bridge enables system solutions to be created for two different applications. The first application involves transporting GbE frames or 10 Mbits/s/100 Mbits/s

Contextual Info: Preliminary Product Brief April 2000 SDE PayloadPlus Software Development Environment The Lucent family of PayloadPlus network processors is designed to support a high degree of programmability at wire speeds. This approach allows hardware designers to build equipment

OR3LP26B

Abstract: OR3T20 ORT8850 7ba2 diode pb7d
Contextual Info: Preliminary Data Sheet April 2001 PayloadPlus /APC UTOPIA Slave Bridge Introduction Features The PayloadPlus/ATM port controller APC universal test and operations PHY interface for ATM (UTOPIA) slave bridge, also known as the PayloadPlus APC wedge (PAW) or the Atlanta™ interface

Agere RSP

Abstract: features of ic 7495 Agere FPP
Contextual Info: Preliminary Product Brief April 2000 NPRSP PayloadPlus Routing Switch Processor Introduction The Routing Switch Processor The Lucent PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full programmability.