M2GL005
Abstract: A2F060
Contextual Info: Power Matters. CO LUT4 C OVFL LO UB ADD_S FPGA and SoC Product +/- Catalog ] A[17:0 D EN RO IN YP EN _SR CLK RST EN X ] C[43:0 SL D SN[43 D ] B[17:0 17 SHIFT >> 17 ASC SEL_C SECURITY RELIABILITY LOW POWER :0] SN-1[43 I N T E G R AT I O N FPGAs SoC FPGAs
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verilog code voltage regulator
Abstract: CORE8051 scaler verilog code verilog code for apb ADC rtl code vhdl code for 16 BIT BINARY DIVIDER microcontroller using vhdl verilog code for adc adc vhdl verilog code for four bit binary divider
Contextual Info: CoreAI Product Summary Synthesis and Simulation Support Intended Use • Analog Interface Control Using a Microprocessor/ Microcontroller and an Actel FusionTM Device • Voltage, Current, and Temperature Monitoring Using a Microprocessor/Microcontroller and an
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16-bitverilog code voltage regulatorcore8051scaler verilog code+7verilog code for apbadc rtl codevhdl code for 16 bit binary dividermicrocontroller using vhdlverilog code for adcadc vhdlverilog code for four bit binary divider
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LF711
Abstract: ADC rtl code tsmc eeprom 0x10500000 LF712 ARM926EJ-S CP15 ICS307 XC2V6000 AN138
Contextual Info: Application Note 138 Using Core Tiles Stand-Alone with IM-LT3 Document number: ARM DAI 0138B Issued: March 2006 Copyright ARM Limited 2005 Application Note 138 Using Core Tiles Stand Alone Copyright 2005 ARM Limited. All rights reserved. Release information
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0138blf711adc rtl codetsmc eeprom+70x10500000lf712arm926ej-scp15ics307xc2v6000an138
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ADC rtl code
Abstract: AC298
Contextual Info: Application Note AC298 Multi-Channel Analog Voltage Comparator in Fusion FPGAs Introduction The Actel FusionTM Programmable System Chip PSC , the world’s first mixed-signal FPGA, integrates mixed-signal analog, Flash memory, and FPGA fabric in a monolithic PSC. Among many other analog and
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ac29812-bitadc rtl code |
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LF712
Abstract: ARM926EJ-S CP15 ICS307 PB926EJ-S XC2V6000 ADC rtl code 0136B DPRAM 128mb T0464FA70
Contextual Info: Application Note 136 Using Core Tiles Stand-Alone Document number: ARM DAI 0136B Issued: January 2006 Copyright ARM Limited 2006 Application Note 136 Using Core Tiles Stand Alone Copyright 2006 ARM Limited. All rights reserved. Release information The following changes have been made to this Application Note.
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0136blf712arm926ej-scp15+6ics307pb926ej-sxc2v6000adc rtl codedpram 128mbt0464fa70
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PB926EJ-S
Abstract: verilog code for ahb bus matrix LF712 AN125 ARM926EJ-S CP15 verilog code arm processor 0x10600000 0xA0100000 0x10400000
Contextual Info: Application Note 125 Adding processors to the PB926EJ-S using Core Tiles Document number: ARM DAI 0125B Issued: January 2006 Copyright ARM Limited 2006 Application Note 125 Adding additional processors to the PB926EJ-S using Core Tiles Copyright 2006 ARM Limited. All rights reserved.
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pb926ej-s0125bverilog code for ahb bus matrixlf712+7an125arm926ej-scp15verilog code arm processor0x106000000xa01000000x10400000
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verilog code voltage regulator
Abstract: verilog code for adc verilog code voltage regulator vhdl verilog code for amba apb bus 16bit microprocessor using vhdl simple ADC Verilog code verilog code for apb vhdl code for Clock divider for FPGA vhdl code for frequency divider APB VHDL code
Contextual Info: P ro du c t Br ie f CoreAI Product Summary Synthesis and Simulation Support Intended Use • Analog Interface Control Using a Microprocessor/ Microcontroller and an Actel FusionTM Device • Voltage, Current, and Temperature Monitoring Using a Microprocessor/Microcontroller and an
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51700066pb-0/3verilog code voltage regulatorverilog code for adcverilog code voltage regulator vhdl+7verilog code for amba apb bus16bit microprocessor using vhdlsimple adc verilog codeverilog code for apbvhdl code for clock divider for fpgavhdl code for frequency dividerapb vhdl code
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RTL 204 601
Abstract: 400x240 conector RJ catalog ShMM-1500R leon3 VME64 alma 8051s CZ80CPU A24D16 RT MIL-STD-1553B ACTEL FPGA
Contextual Info: Solutions and IP Catalog Improve Time-to-Market and Reduce Risk March 2010 Table of Contents Introduction 3 Power Management Solutions Mixed-Signal Power Manager MPM 4 System Management Solutions Pigeon Point Systems 5 Motor Control Solutions 6 Display Solutions
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core8051score10/100core429core1553brm+14core1553brtcore1553brt-ebrcore1553bbccoreaes128rtl 204 601400x240conector rj catalogshmm-1500rleon3vme64 alma8051scz80cpua24d16rt mil-std-1553b actel fpga
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LFE3-70EA-6FN672C
Contextual Info: JESD204A IP Core User’s Guide December 2010 IPUG91_01.3 Table of Contents Chapter 1. Introduction . 3 Introduction . 3
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jesd204aipug91lfe3-70ea-6fn672cd-2010+303lsp1latticeecp3-17/35/70/95/150jesd-204a-e3-u
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lvds to eDP
Abstract: qpsk implementation using verilog EDA 2500 manual LSI gigablaze "ASIC Products Databook" vhdl code hamming oak dsp EDP LVDS BZ75 LSI Logic EPBGA
Contextual Info: G10 -p Deep Submicron ASIC Technology Datasheet The G10-p cell-based CMOS ASIC technology is the highest performance, highest density 3.3 V product in LSI Logic’s portfolio, and supports consumer, computer, and communications applications. The G10-p ASIC product combined with specialized cores enable optimized
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g10tm-pg10-p35-micronlvds to edp+9qpsk implementation using verilogeda 2500 manuallsi gigablazeasic products databookvhdl code hammingoak dspedp lvdsbz75lsi logic epbga
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vhdl coding for analog to digital converter
Abstract: analog to digital converter vhdl coding analog to digital converter vhdl coding on soft digital to analog converter vhdl coding CORE8051 vhdl code for digital to analog converter 4460 MOSFET ADC rtl code ieee embedded system projects eeprom tutorial
Contextual Info: Fusion Design Flow Tutorial Actel Corporation, Mountain View, CA 94043 2005 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 502-00064-0 Release: December 2005 No part of this document may be copied or reproduced in any form or by any means
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vhdl coding for analog to digital converteranalog to digital converter vhdl codinganalog to digital converter vhdl coding on softdigital to analog converter vhdl coding+6core8051vhdl code for digital to analog converter4460 mosfetadc rtl codeieee embedded system projectseeprom tutorial
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AMBA AXI to APB BUS Bridge verilog code
Abstract: AXI2APB bridge verilog code Cortex R4 axi2apb bridge AXI2APB ISC307 verilog code for ahb bus matrix AMBA AXI to AHB BUS Bridge verilog code axi to apb bridge axi bridge
Contextual Info: * Application Note 217 Using a CT-R4F with the RealViewTM Emulation Baseboard Document number: ARM DAI 0217A Issued: April 2009 Copyright ARM Limited 2009 Application Note 217 Using a CT-R4F with EB Copyright 2009 ARM Limited. All rights reserved. Release information
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xc2v6000amba axi to apb bus bridge verilog codeaxi2apb bridge verilog codecortex r4+7axi2apb bridgeaxi2apbisc307verilog code for ahb bus matrixamba axi to ahb bus bridge verilog codeaxi to apb bridgeaxi bridge
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ARCHITECTURE OF ARM 7 TDMA
Abstract: hard driver ic oki packaging video phone H263 audio adc dac H.263 encoder chip g.723.1 codec chip TSMC Flash IP
Contextual Info: Semiconductor Business With a Customer Perspective - SPA As A Solution for System on Chip - May 4, 1998 Katsumasa Shinozuka Senior Managing Director Oki Electric Industry Co., Ltd. 1 Outline 1. Industry Paradigm Shift • IT Industry Evolution • Diversified Customer Needs
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architecture of arm 7 tdmahard driver icoki packagingvideo phone+5h263audio adc dach.263 encoder chipg.723.1 codec chiptsmc flash ip
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ADC rtl code
Abstract: scaler verilog code A3P600 dac a3p600 verilog code lcd
Contextual Info: Overview iW-Video Scaler converts the video signals from one resolution to another resolution. This core can be used to convert low resolution to high or high resolution to low. Features X X X X X Up Scaling by any value from 1 to 4 Down Scaling by any value from 1 to 16
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a3p600agl600adc rtl codescaler verilog code+2dac a3p600verilog code lcd
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STK 2028
Abstract: RTL 2832 STK 4133 II gc 7137 ad STK 5333 stk 5392 stk 5490 stk 2265 STK 5474 STK 4197
Contextual Info: Mon Feb 6 10:03:42 1995 Page 1 'MENSCH COMPUTER ROM SOFTWARE' 'IRQVCTRS.ASM-IRQ VECTOR EQUATES FOR WDC65C265' 2500 A.D. 65816 Macro Assembler - Version 5.01g -Input Filename : irom2.asm Output Filename : irom2.obj
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wdc65c265stk 2028rtl 2832stk 4133 ii+7gc 7137 adstk 5333stk 5392stk 5490stk 2265stk 5474stk 4197
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rtl 8112
Abstract: 65C816
Contextual Info: March 23, 2009 W65C816S 8/16–bit Microprocessor WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any
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DRM003
Abstract: M68HC908GP32 MC68HC908GP32 microcontroller 10uf 25V electrolytic capacitor 8304MHZ SJA1000 MC68HC980 motorola hc08 schematic programmer MPC5556 MC68HC908 32 pin
Contextual Info: 68HC08M6 HC08M68HC 8M68HC08M DRM003/D Parallel or Serial CAN Connection Using External CAN Standalone CAN Controllers with the Motorola M68HC908 Embedded FLASH Microcontrollers Designer Reference Manual blank Parallel or Serial CAN Connection Using External CAN Standalone CAN
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68hc08m6hc08m68hc8m68hc08mdrm003/d+14m68hc908d-77743mc33388mc68hc08as60drm003m68hc908gp32mc68hc908gp32 microcontroller10uf 25v electrolytic capacitor8304mhzsja1000mc68hc980motorola hc08 schematic programmermpc5556mc68hc908 32 pin
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vhdl code for ARINC
Abstract: vhdl code for rs232 receiver using fpga DEI1070 ARINC 568 Line DRiver vhdl code for rs232 receiver DD-03182 KEYPAD interface lcd verilog UART using VHDL rs232 driver binary to lcd verilog code RX1L
Contextual Info: ARINC 429 Bus Interface Product Summary Core Deliverables • Intended Use • ARINC 429 Transmitter Tx • ARINC 429 Receiver (Rx) Key Features • Supports ARINC Specification 429-16 • Configurable up to 16 Rx and 16 Tx Channels • • – Compiled RTL Simulation Model, Compliant
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vhdl code for arincvhdl code for rs232 receiver using fpgadei1070arinc 568 line driver+6vhdl code for rs232 receiverdd-03182keypad interface lcd veriloguart using vhdl rs232 driverbinary to lcd verilog coderx1l
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AMBA AXI to APB BUS Bridge vhdl code
Abstract: PrimeCell AXI Configurable Interconnect PL300 Implementation Guide AMBA AXI to AhB BUS Bridge vhdl code PL081 AMBA AXI to AHB BUS Bridge verilog code axi wrapper 0x10018000 CT926EJ-S LF712 tsmc 0.18um
Contextual Info: $SSOLFDWLRQ1RWH Using a CT7TDMI, CT926EJ-S or CT1136JF-S Core Tile with an Emulation Baseboard Document number: ARM DAI 0148D Issued: October 2007 Copyright ARM Limited 2007 $SSOLFDWLRQ1RWH
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ct926ej-sct1136jf-s0148damba axi to apb bus bridge vhdl code+8primecell axi configurable interconnect pl300 implementation guideamba axi to ahb bus bridge vhdl codepl081amba axi to ahb bus bridge verilog codeaxi wrapper0x10018000lf712tsmc 0.18um
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t-con Application Note
Abstract: 8XC752
Contextual Info: Philips Components-Signetics Application Specific Product Section 3 - 80C51 family derivatives 8XC752 OVERVIEW The Signetics 83C752/87C752 is a single-chip control oriented microcontroller fabricated with Signetics high-density CMOS technology minimizing CMOS latch-up sensi
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80c518xc75283c752/87c75260c51+463c75283c75183c752t-con application note
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ARM1156T2F-S
Abstract: verilog code for ahb bus matrix ARM1176JZF-S arm1176 SP810 AMBA AXI to AHB BUS Bridge verilog code ARM1176JF ARM1176JFZ-S lcd mp4 axi to apb bridge
Contextual Info: Application Note 177 Using a CT1176JZF-S with the RealViewTM Emulation Board Document number: ARM DAI 0177A Issued: April 2007 Copyright ARM Limited 2007 Application Note 177 Using a CT1176JZF-S with EB Copyright 2007 ARM Limited. All rights reserved. Release information
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ct1176jzf-sxc2v6000ct1176arm1156t2f-s+9verilog code for ahb bus matrixarm1176jzf-sarm1176sp810amba axi to ahb bus bridge verilog codearm1176jfarm1176jfz-slcd mp4axi to apb bridge
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16 QAM modulation verilog code
Abstract: 4 QAM modulator demodulator circuitry verilog code for lms adaptive equalizer cs3810 verilog code for TCM decoder VHDL Coding for Pulse Width Modulation vhdl coding for error correction and detection LMS adaptive filter model for FPGA vhdl CS-3810 CS3710
Contextual Info: CS3810 TM 32 QAM Demodulator Virtual Components for the Converging World The CS3810 32 QAM broadband wireless demodulator core has been developed to provide an efficient and highly optimized solution for wireless data networks. Combined with the CS3710 32 QAM modulator core data
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cs3810cs3710155mbpscs5200+9ds381016 qam modulation verilog code4 qam modulator demodulator circuitryverilog code for lms adaptive equalizerverilog code for tcm decodervhdl coding for pulse width modulationvhdl coding for error correction and detectionlms adaptive filter model for fpga vhdlcs-3810
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rtl 8112
Abstract: 65C816 6502 microprocessor
Contextual Info: May 16, 2007 W65C816S 8/16–bit Microprocessor WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made to verify
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w65c816srtl 811265c8166502 microprocessor |
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ADC AD94338
Abstract: AN393 AN394 EP2S180 SLP-50 Filter Noise matlab adc matlab code
Contextual Info: DSP Development Kit, Stratix II Professional Edition Getting Started User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com P25-36000-00 Development Kit Version: 1.0.0 Document Version: 1.0.0 Document Date: August 2005 Copyright 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
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p25-36000-0012-bitadc ad94338an393+5an394ep2s180slp-50filter noise matlabadc matlab code
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