ABI ABN Search Results

ARMv7-M Architecture Reference Manual

Abstract: ARMv5 ARM1136J-S ARM1156T2F-S ARM926EJ-S ARM946E-S how to reverse float variable in java 0043C
Contextual Info: Run-time ABI for the ARM architecture Run-time ABI for the ARM Architecture Document number: ARM IHI 0043C, current through ABI release 2.08 Date of Issue: 19th October 2009 Abstract This document defines a run-time helper-function ABI for programs written in ARM-Thumb assembly language, C,

ULEB128

Abstract: RPB-6
Contextual Info: Itanium Software Conventions and Runtime Architecture Guide May 2001 Document Number: 245358-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no

M12L128168A

Abstract: M12S128168A M12S128168A-10TG
Contextual Info: ESMT M12S128168A Revision History Revision 1.0 Nov. 09, 2006 -Original Elite Semiconductor Memory Technology Inc. Publication Date: Nov. 2006 Revision: 1.0 1/44 ESMT M12S128168A 2M x 16 Bit x 4 Banks SDRAM Synchronous DRAM FEATURES ORDERING INFORMATION y

Contextual Info: ESMT M52D64322A Revision History Revision 1.0 Jan. 19, 2007 -Original Revision 1.1 (Mar. 03, 2007) - Delete BGA ball name of packing dimensions Revision 1.2 (Oct. 08, 2007) - Modify DC/AC characteristics Revision 1.3 (Mar. 11, 2008) - Modify ICC spec - Modify tRC(min), tRFC(min), tSAC(max), tSS(min), tSH(min), and tSHZ(max)

Contextual Info: ESMT M52D64164A Revision History Revision 1.0 Jan. 15, 2007 -Original Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions Revision 1.2 (Oct. 08, 2007) - Modify DC/AC characteristics Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

M12L2561616A-7TI

Contextual Info: ESMT M12L2561616A Operation Temperature Condition -40~85°C 4M x 16 Bit x 4 Banks SDRAM Synchronous DRAM FEATURES y y y y y y y y y ORDERING INFORMATION JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs

Contextual Info: ESM T M12L128168A 2N Operation Temperature Condition -40°C~85°C SDRAM 2M x 16 Bit x 4 Banks Synchronous DRAM FEATURES „ „ „ „ „ „ „ „ „ JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs

Contextual Info: ESM T M12L2561616A 2K Operation Temperature Condition -40 C~85 C SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES „ „ „ „ „ „ „ „ „ ORDERING INFORMATION JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation

M52S128168A

Abstract: M52S128168A-10TG
Contextual Info: ESMT M52S128168A Revision History Revision 1.0 May. 29, 2007 -Original Revision 1.1 (Oct. 08, 2007) -Add Speed -7 spec. -Modify Icc spec Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.1 1/47 ESMT M52S128168A Mobile SDRAM

1M x 16-Bit x 4 Banks synchronous DRAM

Contextual Info: ESMT M52S64164A SDRAM 1M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y y ORDERING INFORMATION 2.5V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency 2 & 3 - Burst Length (1, 2, 4, 8 & full page)

Contextual Info: ESMT M52L64164A SDRAM 1M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y y ORDERING INFORMATION 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency 2 & 3 - Burst Length (1, 2, 4, 8 & full page)

Contextual Info: ESMT M52D2561616A 2F Mobile SDRAM 4M x 16 Bit x 4 Banks Mobile Synchronous DRAM ORDERING INFORMATION FEATURES           1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs

Contextual Info: ESMT M12L128168A 2L Operation Temperature Condition -40°C~85°C SDRAM 2M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs

Contextual Info: ESMT M52D64164A Revision History Revision 1.0 Jan. 15, 2007 -Original Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions Revision 1.2 (Oct. 08, 2007) - Modify DC/AC characteristics Revision 1.3 (Jan. 11, 2008) - Modify ICC spec - Modify tRC(min), tRFC(min), tSAC(max), tSS(min), tSH(min) and tSHZ(max)

Contextual Info: ESMT M52D64164A Mobile SDRAM 1M x 16 Bit x 4 Banks Mobile Synchronous DRAM FEATURES y y y y y y y y y y ORDERING INFORMATION 1.8V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency 2 & 3

Contextual Info: ESM T M52D128168A 2E Mobile SDRAM 2M x 16 Bit x 4 Banks Mobile Synchronous DRAM ORDERING INFORMATION FEATURES „ „ „ „ „ „ „ „ „ „ 1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs

Contextual Info: ESM T M12L128168A 2L Operation Temperature Condition -40 C~85 C SDRAM 2M x 16 Bit x 4 Banks Synchronous DRAM FEATURES „ „ „ „ „ „ „ „ „ JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs

M12L2561616A-5TG2S

Contextual Info: ESMT M12L2561616A 2S SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y y ORDERING INFORMATION JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 )

Contextual Info: ESMT M52D128168A 2E Mobile SDRAM 2M x 16 Bit x 4 Banks Mobile Synchronous DRAM ORDERING INFORMATION FEATURES y y y y y y y y y y 1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3)

SDRAM

Abstract: M12L128168A-5TG M12L128168A6TG2N m12l128168a-7tg
Contextual Info: ESMT SDRAM M12L128168A 2N 2M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page )

M12L2561616A-7TG2K

Contextual Info: ESMT M12L2561616A 2K SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y ORDERING INFORMATION JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 )

elite ups

Contextual Info: ESMT M52L64164A Operation Temperature Condition -40~85°C Mobile SDRAM 1M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y y ORDERING INFORMATION 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs

SDRAM

Abstract: M12L2561616A-5T 54-lead M12L2561616A
Contextual Info: ESMT M12L2561616A 2A Automotive Grade SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y GENERAL DESCRIPTION JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs

Contextual Info: ESM T SDRAM M12L128168A 2L 2M x 16 Bit x 4 Banks Synchronous DRAM FEATURES „ „ „ „ „ „ „ „ „ JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 )