A7R TRANSISTOR Search Results

Contextual Info: electronic June 1992 M 67024 DATA SHEET_ 4 k x 16 CMOS DUAL PORT RAM FEATURES . FAST ACCESS TIME : 35 NS TO 55 NS 30 NS PRELIMINARY FOR COMMERCIAL ONLY . WIDE TEMPERATURE RANGE: - 55°C TO + 125°C . 67024 L LOW POWER 67024 V VERY LOW POWER

Contextual Info: CY7C130, CY7C130A CY7C131, CY7C131A 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Functional Description Features • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power

Contextual Info: Temic Semiconductors 2 K x 8 CMOS Dual Port RAM M67132/M67142 Description The M67132/67142 are very low power CMOS dual port static RAMs organized as 2048 x 8. They are designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or

CY7C136-55JC

Contextual Info: CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Functional Description Features • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 2K x 8 organization ■ 0.65 micron CMOS for optimum speed and power

431AM

Abstract: 6 PIN 36AA
Contextual Info: MTE D • SöböMSb D G O in i IIIÌmÌIII I V l M P Advance Information HI-REL DATA SHEET_ 430 — ■ NMHS MATRA T = ^ - ^ - /Z M H S January 1991 M 671 32/M 67142 2 kx 8 CMOS DUAL PORT RAM FEATURES . . . ACCESS TIME MILITARY : 35 TO 55 ns max .

CY7C136E

Abstract: CY7C131AE-15JXI CY7C136AE-55NXI
Contextual Info: CY7C131E, CY7C131AE CY7C136E, CY7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization

Contextual Info: M ill PRELIMINARY DATA SHEET_ HM 65688A 16 K x 4 ULTIMATE CMOS SRAM FEATURES . ACCESS TIME COMMERCIAL : 35/45 ns max MILITARY/INDUSTRIAL : 45/55 ns (max) . VERY LOW POWER CONSUMPTION ACTIVE : 175.0 mW (typ) STANDBY : 0.5 |lW (typ)

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.

Contextual Info: CY7C09269V/79V/89V CY7C09369V/89V 3.3 V 16 K / 32 K / 64 K x 16 / 18 Synchronous Dual-Port Static RAM 3.3 V 16 K / 32 K / 64 K × 16 / 18 Synchronous Dual-Port Static RAM Features • ■ True dual-ported memory cells that allow simultaneous access of the same memory location

Contextual Info: CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K x 8 Asynchronous Dual-Port Static RAM CY7C144AV CY7C006AV 3.3 V 8 K / 16 K × 8 Asynchronous Dual-Port Static RAM 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM Features

Contextual Info: CY7C024AV/024BV/025AV/026AV 3.3 V 4 K / 8 K / 16 K x 16 Dual-Port Static RAM 3.3 V 4 K / 8 K / 16 K × 16 Dual-Port Static RAM Features • Automatic power down ■ True dual-ported memory cells which enable simultaneous access of the same memory location

Contextual Info: CY7C008V CY7C018V CY7C009V CY7C019V 3.3 V 64 K/128 K x 8/9 Dual-Port Static RAM CY7C008V/009V CY7C018V/019V 3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM 3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM Features • Fully asynchronous operation ■ Automatic power-down

Contextual Info: CY7C008V CY7C018V CY7C009V CY7C019V 3.3 V 64 K/128 K x 8/9 Dual-Port Static RAM CY7C008V/009V CY7C018V/019V 3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM 3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous

L06lC

Abstract: 67132
Contextual Info: IH M DATA SHEET L 6 7 1 3 2 /L 67142 2 Kx8 CMOS DUAL PORT RAM 3.3 VOLT FEATURES . . . • ON CHIP ARBITRATION LOGIC BUSY OUTPUT FLAG ON MASTER BUSY INPUT FLAG ON SLAVE FULLY ASYNCHRONOUS OPERATION FROM EITHER PORT . BATTERY BACKUP OPERATION: 2 V DATA RETENTION

M67130

Abstract: M67140 P883
Contextual Info: M67130/M67140 1 K  8 CMOS Dual Port RAM Introduction The M 67130/67140 are very low power CMOS dual port static RAMs organized as 1024 x 8. They are designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or

Contextual Info: CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833V FLEx18 3.3 V 128 K / 256 K / 512 K x 18 Synchronous Dual-Port RAM FLEx18™ 3.3 V 128 K / 256 K / 512 K × 18 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access

M67130

Abstract: M67140 67140
Contextual Info: M 67130/M 67140 MATRA MHS 1 K x 8 CMOS Dual Port RAM Introduction The M 67130/67140 are very low power CMOS dual port static RAMs organized as 1024 × 8. They are designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or

Contextual Info: Tem ic M 67132/M 67142 MATRA MHS 2 K x 8 CMOS Dual Port RAM Description The M 67132/67142 are very low power CMOS dual port static RAMs organized as 2048 x 8. They are designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or

M67134

Abstract: L200-220
Contextual Info: M 671342 MATRA MHS 4K x 8 CMOS Dual Port RAM with Semaphore Introduction The M 671342 is a very low power CMOS dual port static RAM organised as 4096 × 8, with full hardware support of semaphore signaling between the two ports. The M671342 device provide two independant ports with

Contextual Info: CY7C02732 K / 64 K x 16 Dual-Port Static RAM CY7C027 CY7C028 32 K / 64 K × 16 Dual-Port Static RAM 32 K / 64 K × 16 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location ■ 32 K × 16 organization CY7C027

Shared resource arbitration

Contextual Info: miMHS PRELIMINARY March 1994 L 67005 DATA SHEET 8 KX 8 CMOS DUAL PORT RAM 3.3 VOLT FEATURES VERSATILE PIN SELECT FOR MASTER OR SLAVE: - M/S= H FOR BUSY OUTPUT FLAG ON MASTER - M/S = L FOR BUSY INPUT FLAG ON SLAVE INT FLAG FOR PORT TO PORT COMMUNICATION FULL HARDWARE SUPPORT OF SEMAPHORE

Contextual Info: Tem ic L 67005 MATRA MHS 8 K x 8 CMOS Dual Port RAM 3.3 Volt Introduction The L 67005 is a very low power CMOS dual port static RAM organized as 8192 x 8. The L 67005 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit or

S2MH

Contextual Info: IHM M 67024 DATA SHEET 4 K x 16 CMOS DUAL PORT RAM FEATURES . FAST ACCESS TIME: 35 NS TO 55 NS 30 NS PRELIMINARY FOR COMMERCIAL ONLY WIDE TEMPERATURE RANGE: - 55 °C TO + 125 °C 67024 L LOW POWER 67024 V VERY LOW POWER SEPARATE UPPER BYTE AND LOWER BYTE CONTROL