A26A Search Results

A26ASBR

Abstract: A-26 A219 SPST A25ASBB
Contextual Info: www.i-t.su info@i-t.su electronics тел: 495 739-09-95, 739-09-96 Кнопочные переключатели серии A2 Ć13.5 резиновый колпачок A26ASBR A26ASBR A25ASBB A219 A219 Серия кнопочных переключателей с очень хорошими электрическими

2561b

Abstract: CPU 314 IFM 8kx1 RAM cy17 ALI chipset fast page mode dram controller CY2254ASC-2 CY27C010 CY82C691 CY82C693
Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support for standard 72-bit-wide DRAM banks Supports non-symmetrical DRAM banks

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024x36x2 Integrated Device Technology, Inc. PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • M aster R eset clears d ata and configures FIFO, Partial R eset clears data but retains configuration settings

Contextual Info: | CMOS Bus-Matching SyncFlFO 256 x 36, 512 x 36,1,024 x 36 dt PRELIMINARY ¡DT723633 IDT723643 Integrated D ev ic e Techno logy, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping IDT723613 64x36 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity FIFO buffering data from Port A

Contextual Info: In te g ra te d D e v i e T e d h n o Jo g y , lie . CMOS Triple Bus SyncFlFO1 With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: There are two errata notices at the end of this data sheet. The May 20 errata describes corrections that have

Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

Contextual Info: 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 • Passive parity checking on each Port • Parity Generation can be selected for each Port • Available in 132-pin plastic quad flat package PQF , or space saving 120-pin thin quad flat package (TQFP)

Contextual Info: Integrated Device Technology, Inc. CMOS Sync BiFlFO With Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 PRELIMINARY IDT723624 IDT723634 IDT723644 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

Contextual Info: |dy Integrated Dev ice Technology, Inc. CMOS Triple Bus SyncFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY I D T y iii ll IDT723646 FEATURES: • Memory storage capacity: IDT723626-256 x 36 x 2 IDT723636-512 x 3 6 x 2 IDT723646-10 2 4 x 3 6 x 2

Contextual Info: Integrated Device TechnoJogy, lie. PRELIMINARY IDT723624 IDT723634 IDT723644 CMOS Sync BiFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

723674

Abstract: IDT723654 IDT723664 IDT723674
Contextual Info: CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2 FEATURES: PRELIMINARY IDT723654 IDT723664 IDT723674 ♦ Port B bus sizing of 36 bits long word , 18 bits (word) and 9 bits (byte) ♦ Big- or Little-Endian format for word and byte bus sizes

ITE 8721

Abstract: fnd 503 7-segment TAA 2761 A 486 motherboard schematic 3860S 486dx isa bios pin assignment RAS 0510 cxd 9897 tn ti77 k244
Contextual Info: ISA/486 C H |p g . CepyTlgtt N ette S o t t r a e C o p y ñ f tt O 1962, a * « * d T e d » a i e s i e * . l w x M t o n i I C o p y r i i h t O 1992 . Q ñ p » » d T c c t n o f a p B » , ! ^ . A B SIduR am i Poned ib UJ5A. Tw dw u U t h w lw lgim iil

pdic cd

Contextual Info: SN74ABT361 3 64 x 36 C L O C K E D F I R ST - I N, F I R S T - O U T M E M O R Y WITH BUS M A T C H IN G AND BYTE S W A P P I N G SC B S 128E -JU LY 1 9 9 2 - REVISED FEBRUARY 1996 F r e e - R u n n i n g C L K A and C L K B Can Be M i c r o p r o c e s s o r I nt er fac e Co nt rol Logic

IDT723623

Abstract: IDT723633 IDT723643 B35b
Contextual Info: CMOS Bus-Matching SyncFIFO 256 x 36, 512 x 36, 1,024 x 36 PRELIMINARY IDT723623 IDT723633 IDT723643 Integrated Device Technology, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:

IDT72V3623

Abstract: IDT72V3653 IDT72V3663 IDT72V3673
Contextual Info: 3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36, 4,096 x 36, 8,192 x 36 FEATURES: ADVANCE INFORMATION IDT72V3653 IDT72V3663 IDT72V3673 ♦ ♦ Retransmit Capability Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings

Contextual Info: CMOS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36 4,096 x 36 8,192 x 36 • • • FEATURES • • • • • • • Memory storage capacity: IDT723653 – 2,048 x 36 IDT723663 – 4,096 x 36 IDT723673 – 8,192 x 36 Clock frequencies up to 83 MHz 8 ns access time

IC51-1324-828

Abstract: IDT723613 IDT72V3613
Contextual Info: IDT72V3613 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 FEATURES: ♦ ♦ ♦ Passive parity checking on each Port Parity Generation can be selected for each Port Available in 132-pin plastic quad flat package PQF , or space saving 120-pin thin quad flat package (TQFP)

CHN 044 VW

Abstract: NB18
Contextual Info: CMOS SyncBiFIFO with Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 IDT723624 IDT723634 IDT723644 • Port B bus sizing ot 36-bits long word , 18-bits (word) and 9-bits (byte) • Big- or Little-Endian tormat tor word and byte bus sizes • Master Reset clears data and contigures FIFO, Partial

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 2 5 6 x 3 6 x 2, 512 x 3 6 x 2, 1,024 x 36 x 2_ FEATURES: • Memory storage capacity: IDT72V3624-256 x 36 x 2 IDT72V3634-512 x 36 x 2 IDT72V3644-1,024x36x2 • Clock frequencies up to 83 MHz 8ns access time

Contextual Info: CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36 FEATURES: • • • • • • • • • Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 Clocked FIFO buffering data from Port A to Port B Clock frequencies up to 83 MHz 8 ns access time

Contextual Info: IDT72V3613 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 • • FEATURES: • • • • • • • • • • • • • 64 x 36 storage capacity FIFO buffering data from Port A to Port B Supports clock frequencies up to 83MHz

723674

Contextual Info: 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 • • • FEATURES • • • • • • • Memory storage capacity: IDT72V3654 – 2,048 x 36 x 2 IDT72V3664 – 4,096 x 36 x 2 IDT72V3674 – 8,192 x 36 x 2 Clock frequencies up to 100 MHz 6.5ns access time

Contextual Info: CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 1,024 x 36 x 2 FEATURES: • • • • • • • • • Memory storage capacity: IDT723626 – 256 x 36 x 2 IDT723636 – 512 x 36 x 2 IDT723646 – 1,024 x 36 x 2 Clock frequencies up to 83 MHz 8ns access time