A1B 260 03 Search Results

81C61

Contextual Info: 1 111111111111111 11111 1 111111111111111 1 111111111111111 1 111111111111111 1 1 1234536787119ABACDEFA1D91111111 1 11111111 1 11111111 1 11 A1C 123314567891A758BCD814E1F3D167D1F1C5A36 AB1DA167 4DE !"#$%168812&' 1291CC1!"#1AABA9

74HCT139

Contextual Info: TECHNICAL DATA IN74LV139 Dual 2-to-4 line decoder/demultiplexer; inverting N SUFFIX PLASTIC The IN74LV139 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HCT139. The74LV139 is dual 2-to-4 line decoder/demultiplexer . This device has two independent decoders, each accepting two binary

74HC139a

Abstract: DL129 LS139 MC54HCXXXAJ MC74HCXXXAD MC74HCXXXAN 74HC139AD
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC139A Dual 1-of-4 Decoder/ Demultiplexer High–Performance Silicon–Gate CMOS The MC54/74HC139A is identical in pinout to the LS139. The device inputs are compatible with standard CMOS outputs; with pullup resistors,

MIL-S-3950

Abstract: 2TL1-12
Contextual Info: if LjJ g: MICRO SWITCH FREEPORT. IL L IN O IS . A OF D IV IS IO N fed . uj LO CNJ C A TA LO G L IS TIN G 2 T L 1 -1 2 SWITCH-T0GGLE U S A HONEYW ELL S E R IE S CHART 1 MFC. CODE »182» T H IS D R A W I N G C O V E R S A P R O P R I E T A R Y I T E M A N D IS T H E P R O P E R T Y O F M IC R O SWI TC H. A D I V I S I O N O F

TC538000F

Contextual Info: s s S b P & & *& *& & & V~'+fr* " * ' w •vi TOS H IB A LfrGIC/NEIIORY* “ trEET r ^0^7240 G 0 2 1 elQ4 1 • T0S2 8M BIT (1 M W O R D X 8 BIT) CM O S M A SK RO M DESCRIPTION The TC538000P/F is a 8,388,608 bits read only memory organized as 1,048,576 words by 8blts.

74hc139a

Contextual Info: MOTOROLA SC 11E 0 § LOGIC OGflCHE*! T | Order this data sheet by MC54HC139A/D MOTOROLA SEM ICONDUCTOR TECHNICAL DATA T - 6 7 - 2 I - 5 Í ' M C54/74HC139A Advanced Information J SU FFIX CERAMIC CA SE 620-09 Dual 1-of-4 Decoder/ Demultiplexer High-Perform ance Silicon-G ate CM OS

Contextual Info: Preliminary KM68V4000B, KM68U4000B Family CMOS SRAM 512Kx8 bit Low Pow er & Low Vcc CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology : 0.4pm CMOS T he K M 68V 4000B and K M 68U 4000B fam ily are • Organization : 512K x 8 fabricated by SAMSUNG’S advanced CM O S process

cs 308

Abstract: KM68U4000A
Contextual Info: KM68U4000A CMOS SRAM ELECTRONICS 512Kx8 bit Low Power & Low Vcc CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology : 0.4 um CMOS • Organization : 512Kx 8 • Power Supply Voltage KM68V4000A Family : 3.3 +/- 0.3V KM68U4000A Family : 3.0 +/- 0.3V

9114 static ram

Abstract: dallas ds1280 a17b 68-PIN DS1280 DS1280Q-68 TD1220
Contextual Info: » A L L A S SEMICONDUCTOR CORP 31E D B HblMlBO 0003*133 0 ES DAL O S 1280 • W toàia^ M M éa^ M ni iii ii ì r -iiiJL.V^-r ¿ « .,- Mt. -«h. . '.riti , , tM . \* ^ * 5 0~7 E i£ a « a 081280 DALLAS 3-Wire to Bytewide Converter Chip semiconductor

LM 3919

Contextual Info: LED HIGH POWER CoB Product Series LED HIGH POWER CoB Product Series Data Sheet Created Date: 02 / 06 / 2013 Revision: 2.0, 05 / 21/ 2013 1 BNC-OD-C131/A4 Created Date : 05/26/2007 Revison : 1.01, 05/26/2008 LED HIGH POWER CoB Product Series 1. Description

IC 4012

Abstract: 4012 IC ci 4012 ALVCH16260 IDT74ALVCH16260 SO56-2 TH4012
Contextual Info: 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER IDT74ALVCH16260 ADVANCE INFORMATION Integrated Device Technology, Inc. 12-bit latched bus multiplexers/transceivers for use in highspeed microprocessor application. These Bus Exchangers support memory interleaving with latched outputs on the B

55AX1000

Abstract: FP-1-35-G-10 FP-1-27-G-10 10A3500 10A35 A3600 1-GUSVT-610 A1B ABB 2-GSVT-48-A 2-GUSVT-410
Contextual Info: Variable Area Flowmeter, Glass Tube Models A3500 & A3600 Specification DataFile •■ Removable metering tube – for range changing or cleaning without removing meter from line ■■ External retaining spring and equal area ends on tube – prevents the tube moving under pressure,

Contextual Info: D S 1647/D S 1S 47P PHELlMiNARY f iA I • A C - Nonvolatile Timekeeping RAM FEATURES PIN ASSIGNMENT DS1647/DS1647P A I6 B 2 A14 §3 A l2 • Clock registers are accessed identical to the static RAM. These registers are resident In the eight top RAM locations.

Contextual Info: CMOS SRAM KM68V1000B, KM68U1000B Family 128Kx8 bit Low Power & Low Vcc CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process T ec h n o lo g y : 0.6 um C M O S T h e K M 6 8 V 1 0 0 0 B and K M 6 8 U 1 0 0 0 B fam ily are fabricated • O rg a n iz a tio n : 1 2 8 K x 8

pin diagram of ic 6260

Contextual Info: FAST CMOS 12- BI T TRI - PORT BUS E X C H A N G E R IDT54/74FCT16260AT/CT/ET IDT54/74FCT162260AT/CT/ET FEATURES: DESCRIPTION: • C o m m o n f e a t ur e s : The F C T 16260A T/C T/E T and the F C T 162260AT/C T/ET Tri-Port Bus Exchangers are high-speed 12-bit latched bus

sel 4039

Contextual Info: 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FE A T U R E S : - 0.5 MICRON CMOS Technology - Typical - ESD > 2000V per MIL-STD-883, Method 3015; tsK o (Output Skew) < 250ps > 200V using machine model (C = 200pF, R = 0)

Contextual Info: 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: - 0.5 MICRON CMOS Technology - Typical tsK o (Output Skew) < 250ps - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) -

Contextual Info: SN65LVDS386/388A/390, SN65LVDT386/388A/390 SN75LVDS386/388A/390, SN75LVDT386/388A/390 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394D – SEPTEMBER 1999 – REVISED MAY 2001 D D D D D D D D D D D Four ’390 , Eight (‘388A), or Sixteen (‘386) Line Receivers Meet or Exceed the

Contextual Info: PRELIMINARY |\/|^ C a O M I 32K X MT2LSYT3264T4/T6 64 SYNCHRONOUS SRAM MODULE SYNCHRONOUS J i n a • m ^ N .a-va ■■ ■ - SRAM MODULE 32K x 64 SRAM 256KB, 3.3V, PIPELINED SYNCHRONOUS BURST, SECONDARY CACHE MODULES FEATURES • • • • PIN ASSIGNMENT Front View

420 Diode 2ba

Contextual Info: 3.3V CMOS 12-BIT TO 24-BIT IDT74ALVCHR162260 MULTIPLEXED D-TYPE ADVANCE LATCH WITH 3-STATE INFORMATION OUTPUTS AND BUS-HOLD FE A T U R E S : - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

IC-7216

Abstract: upd6130 4608 kHz EH 002
Contextual Info: M O S IN T E G R A T E D C IR C U IT ELECTRON B E V I C E ^ T 1 . ^ /¿PD6130 MSK REMOTE CONTROL SENDER/RECEIVER 1C CMOS 1C The /nPD6130 is a remote control IC that implements sending and receiving the M inim um S h ift Keying MSK signal. The ¿1PD6130 is composed of 1 K steps o f ROM (10 bits/step), 32 words of RAM (5 bits/w ord), 4 -bit parallel processing

Contextual Info: PRELIMINARY * <|l ~ n n M » MT2LSYT3264T1/T2 32K x 64 SYNCHRONOUS SRAM MODULE 32K x 64SRAM SYNCHRONOUS . . . O r lA IV I H ll/N r M II •— 256KB, 3.3V, FLOW-THROUGH SYNCHRONOUS BURST, SECONDARY CACHE MODULES n /IU D U L b FEATURES OPTIONS 160-Lead DIMM

Contextual Info: PRELIMINARY M im O N I MT2LSYT3272T1/T2, MT4LSY6472T1/T2 32K, 64K X 72 SYNCHRONOUS SRAM MODULE SYNCHRONOUS SRAM MODULE 32K, 64K x 72 SRAM 256KB/512KB, 3.3V, FLOW-THROUGH SYNCHRONOUS BURST, SECONDARY CACHE MODULES FEATURES PIN ASSIGNMENT Front View 160-lead, dual-in-line memory module (DIMM)

TC58256FT

Contextual Info: TOSHIBA TENTATIVE TC58256FT/DC TOSHIBA M O S DIGITAL INTEGRATED CIRCUIT SILICON GATE CM O S 256-MBIT 32M X 8 BITS CMOS NAND E2PROM DESCRIPTION The TC58256FT/DC {« a single S.S-V 258-Mbit (27fl,824,O04) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E ’FROM) organized as 528 bytes X 32 pages X 2048 blocks.