A06 N03 Search Results

DH11

Abstract: DH21 DH23 b09 n03 DH19 dh17 A09 N03 Dh14 dh28 Dh29
Contextual Info: OFFICIAL - 9/17/97 CBGA Footprints Rev. F 603 Family CBGA C16 E04 D13 F02 D14 G01 D15 E02 D16 D04 E13 G02 E15 H01 E16 H02 F13 J01 F14 J02 F15 H03 F16 F04 G13 K01 G15 K02 H16 M01 J15 P01 L02 K04 C01 B04 B03 B02 A04 B07 J04 A10 L01 B06 E01 D08 A06 D07 B01 B05

RTU A08

Abstract: 308-815
Contextual Info: GE C P L E S S E Y !SEMICONDUCTORS I A DVAN CE INFORMATION 3088-1.5 December 1991 CT2566 MIL-STD-1553 TO MICROPROCESSOR INTERFACE UNIT G P S C T 2 5 6 6 M IL -S T D -1 5 5 3 to M ic ro p ro c e s s o r Interface Unit sim plifies the CPU to 1553 Data Bus interface.

RTU A08

Abstract: RTU A01 4k x 4 ram microprocessor types intel 8080 63d08 MARK A03 d1137 d1541 Z8000
Contextual Info: GEC P L E S S E Y A D VAN CE INFORMATION I S E M I C O N D U C T O R S ¡_ 3 088-1.5 Decem ber 1991 CT2566 MIL-STD-1553 TO MICROPROCESSOR INTERFACE UNIT G P S C T 2 5 6 6 M IL -S T D -1 5 5 3 to M ic ro p ro c e s s o r Interface Unit sim plifies the CPU to 1553 Data Bus interface.

A09 N03

Abstract: a06 n03 RTU A08 b09 n03 ddc bus-66312 BUS-66312 66312
Contextual Info: 000 BUS-66312 ILC DATA DEVICE CORPORATION_ _ _ MIL-STD-1553 TO MICROPROCESSOR INTERFACE UNIT F E A TU R E S • C O M P A T IB L E W ITH M IL-S T D -1750 C PU s • C O M P A T IB L E W ITH M O TO R O LA , INTEL, A N D Z IL O G C PU s • C O M P A T IB L E W ITH D D C

BUS-66300

Contextual Info: QQQ BUS-66312 ILC D ATA D E V IC E CO RPO RATIO N _ MIL-STD-1553 TO MICROPROCESSOR INTERFACE UNIT REFER TO BUS-61553 FOR MEMORY MANAGEMENT DESCRIPTION AND TIMING. DESCRIPTION DDC's BUS-66312 M IL-S TD -1553 to M icroprocessor Interface Unit sim plifies the CPU to 1553 Data Bus interlace

dh28 560

Abstract: A09 N03 10C6 Diode cheetah dh28 DH07 11B8 DL03 5d7 switching regulator OVDD14
Contextual Info: 8 7 6 5 4 3 2 1 CHEETAH4.0 CPU D D CARD SCHEMATICS C C 1/15/98 B B THIS DOCUMENT CONTAINS PRELIMINARY INFORMATION AND IS SUBJECT TO CHANGE BY IBM WITHOUT NOTICE. IBM ASSUMES NO RESPONSIBILITY OF LIABIALITY FOR ANY USE OF THE INFORMATION CONTAINED HEREIN. NOTHING IN THIS DOCUMENT SHALL

b09 n03

Abstract: RTU A08 b04 n03 A09 N03 RTU A01 1553 bus controller b04 n06 a13 trans a06 n03
Contextual Info: 000 BUS-65612 ILC DATA DEVICE CORPORATION«_ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACTFACTORY AND BUS MONITOR FOR MORE INFORMATION FEATURES DESCRIPTION The B U S -6561 2isa 16M H z single chip dual re dund ant M IL-S TD -1553 Bus Controller BC , Remote Terminal Unit

dh03

Abstract: DH07 DH09 AB-04 MDATA62 dh23 AD-05 T14 N03 w04 68 mark w06
Contextual Info: . CPC700 Memory Controller and PCI Bridge Features map essential to making it appear like a device but does not preclude it from being a host. • PowerPC 60x/7xx bus. • 66.66 MHz. • 83.33 MHz. • Synchronous DRAM interface operates at the processor bus speed with support for ECC.

DH-04

Contextual Info: . CPC700 Memory Controller and PCI Bridge Features map essential to making it appear like a device but does not preclude it from being a host. • PowerPC 60x/7xx bus. • 66.66 MHz IBM25CPC700BB3B66 . • 83.33 MHz (IBM25CPC700BB3B83). • Synchronous DRAM interface operates at the

A09 N03

Abstract: b09 n03 b04 n03 b06 n03 65612
Contextual Info: 000 BU-65612 lue DATA DEVICE CORPORATION _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL Contact Factory For BUS-65612 AND BUS MONITOR CMOS SOS Version DESCRIPTION The BU-65612 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Con­ troller (BC), Remote Terminal Unit (RTU),

K0212

Abstract: A09 N03
Contextual Info: 000 BUS-65612 ILC DATA DEVICE CORPORATION_ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACT FACTORY AND BUS MONITOR FOR MORE INFORMATION FEATURES DESCRIPTION The BUS-65612 is a 16 MHz single chip dual redund ant M IL-S TD -1553 Bus C ontroller BC , Remote Terminal Unit

b09 n03

Abstract: MDATA62 DH03 DH-04 aa09
Contextual Info: . CPC700 Memory Controller and PCI Bridge Features map essential to making it appear like a device but does not preclude it from being a host. • PowerPC 60x/7xx bus. • 66.66 MHz IBM25CPC700BB3B66 . • 83.33 MHz (IBM25CPC700BB3B83). • Synchronous DRAM interface operates at the

Contextual Info: D _ DC i/:'1! Z,W ; VJ«- BUS-65612 ILC DATA DEVICE CORPORATION _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACT FACTORY AND BUS MONITOR FOR MORE INFORMATION FEATURES DESCRIPTION The BUS-65612 is a 16 MHz single chip dual re dund ant M IL-S TD -1553 Bus

b09 n03

Abstract: A09 N03 B07 P03
Contextual Info: 1.6 PowerPC 604e Microprocessor Pinout Listings Table 10 provides the pinout listing for the 604e CBGA package. Table 10. Pinout Listing for the CBGA Package Signal Name Pin Number Active I/O A[0—31 ] C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13,

IBM25CPC700DB3A83

Abstract: ae02 marking DH06 marking CODE W04 CPC700 DH02 IBM25CPC700DB3A83Z dh03 dh04 DL05
Contextual Info: . CPC700 Memory Controller and PCI Bridge Features • PowerPC 60x/7xx bus. • 66.66 MHz • 83.33 MHz • Synchronous DRAM interface operates at the processor bus speed with support for ECC. • PCI Revision 2.1 Compliant Interface. • Supports independent primary and secondary

Contextual Info: BBS BU-65612 ILC DATA DEVICE CORPORATION«— MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL Contact Factory For BUS-65612 AND BUS MONITOR CM O S S O S Version FEATURES DESCRIPTIO N The BU-65612 ¡s a 16 M H z single chip dual redundant M IL-ST D -1 553 B u s C o n ­

AA09

Abstract: AA07 t04 68 3 pin controller IBM25CPC700CB3B66 DH06 A09 N03 CPC700 IBM25CPC700BB3B66 IBM25CPC700BB3B83 DH07
Contextual Info: . CPC700 Memory Controller and PCI Bridge Features map essential to making it appear like a device but does not preclude it from being a host. • PowerPC 60x/7xx bus. • 66.66 MHz IBM25CPC700BB3B66 . • 83.33 MHz (IBM25CPC700BB3B83). • Synchronous DRAM interface operates at the

IBM25CPC700DB3A83

Abstract: DH27 DH06 DH07 IBM25CPC700DB3A83Z ae02 marking dh03 marking CODE W04 ae09 MARKING CODE k07
Contextual Info: . CPC700 Memory Controller and PCI Bridge Features • PowerPC 60x/7xx bus. • 66.66 MHz • 83.33 MHz • Synchronous DRAM interface operates at the processor bus speed with support for ECC. • PCI Revision 2.1 Compliant Interface. • ROM/SRAM/External peripheral controller.

b09 n03

Abstract: A09 N03 YA11 D803 yb05 L0722 L0623 k0312 apl 117 YA16
Contextual Info: Am29C334 CMOS Four-Port Dual-Access Register File PRELIMINARY 64 x 18 Bit Wide Register File The Am29C334 is a 64 x 18-bit, dual-access RAM with two read ports and two write ports. Pipelined Data Path The Am29C334 can be configured to support either a non-pipelined data path similar to the Am29334 or a

A09 N03

Abstract: a06 n03
Contextual Info: □00 BUS-65612 ILC DATA DEVICE CORPORATION _ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACTFACTORY AND BUS MONITOR FOR MORE INFORMATION FEATURES DESCRIPTION T h e B U S -6 5 6 1 2 is a 16 M H z sin g le c h ip All m e ssa g e tra n sfe r tim in g , D M A, and

Contextual Info: 000 BUS-65612 ILC DATA DEVICE CORPORATION_ _ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACT FACTORY AND BUS MONITOR FOR MORE INFORMATION FEA TU R ES DESCRIPTION T h e B U S -6 5 6 1 2 is a 16 M H z sin g le ch ip d u a l r e d u n d a n t M IL -S T D -1 5 5 3 B u s

k0312

Abstract: yb06 YB04 YA16 apl 117 yb07 y802 AWa3 74N10 V18-Y3S
Contextual Info: Am29C334 CMOS Four-Port Dual-Access Register File PRELIMINARY • 64 x 18 Bit W ide R egister File The Am29C334 is a 64 x 18-bit, dual-access RAM with tw o read ports and two write ports. Pipelined Data Path The Am 29C334 can be configured to support either a

AB29 DIODE

Contextual Info: Electrical Characteristics 12.1 Signal Specifications 12.1.1 Unused Pins 12 For reliable operation, always connect unused inputs to an appropriate signal level. Unused AGTL+ inputs should be connected to VTT. Unused active low 3.3V-tolerant inputs should be

Contextual Info: Electrical Characteristics 12.1 Signal Specifications 12.1.1 Unused Pins 12 For reliable operation, always connect unused inputs to an appropriate signal level. Unused A G TL+ inputs should be connected to V 7 7 . Unused active low 3.3 V-tolerant inputs should be