Y100H Search Results

SY100H841L

Abstract: SY10H841L
Contextual Info: O 3 3V SING LE SUPPLY Q UAD C Y h lC D flY PECL-TO -TTL W ITH O U TPU T ENABLE S E M IC O N D U C T O R C lo c k w o rk s P R E LIM IN A R Y S Y 10H 841L S Y100H 841L D ES C R IPTIO N FE A TU R E S • 3.3V power supply ■ Translates positive ECL to TTL PECL-to-TTL

SY100H603

Abstract: SY10H603 ICCZ80
Contextual Info: * 9-BIT LATCHED ECL-TO-TTL SYNERGY S E M IC O N D U C T O R FEA TU R E S t S Y10H 603 S Y100H 603 D ES C R IPTIO N 9-bit ideal for byte-parity applications 3-state TTL outputs The S Y 10/100H 603 are 9-bit, dual supply ECL-to-TTL translators. Devices in the Synergy 9-bit translator series

SY100H842L

Abstract: SY10H842L SY10H842ZC SY10H842ZCTR
Contextual Info: ‘ÌOOIBÙI * 000E325 Tfl3 3.3V SING LE SUPPLY Q UAD P EC L-TO -TTL W ITH LATCHED O UTPUT ENABLE C V W C D /^ V S E M IC O N D U ^ -O R p r e u m ^n a RY S Y10H 842L S Y100H 842L D ES C R IPTIO N F E A TU R E S • 3.3V power supply ■ Translates positive ECL to TTL PECL-to-TTL

Contextual Info: .M i P ln r k W n r k c ^ 3.3V SINGLE SUPPLY 1:9 PECL-TO-TTL SYNERGY PRELIMINARY SY10H641L Y100H641L SEM ICONDUCTOR FEATURES DESCRIPTION • 3 .3 V p o w e r s u p p ly ■ P E C L -to -T T L v e rs io n o f p o p u la r E C L in P S E111 ■ G u a ra n te e d lo w s k e w s p e c ific a tio n

Contextual Info: * REGISTERED HEX TTL-TO-PECL TRANSLATOR SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • Differential 50£2 ECL outputs ■ Choice between differential PECL or TTL clock input ■ Single +5V power supply ■ V bb output for single-ended use ■ Multiple power and ground pins to minimize noise

SD013

Abstract: SY10H843ZC
Contextual Info: SINGLE SUPPLY PECL-TTL 1:4 CLOCK DRIVER Clockworks PRELIMINARY SY10/100H843 DESCRIPTION FEATURES Translates positive ECL to TTL PECL-TTL 300ps pin-to-pin skew Guaranteed skew spec Differential internal design for increased noise immunity and stable threshold inputs

Contextual Info: A SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE e V W C D / 'V sE ^ ooXd u c to r C lo c k w o rk s SY10H842 Y100H842 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew

H600

Abstract: SY10H641A
Contextual Info: * SINGLE SUPPLY 1:9 PECL-TO-TTL SYNERGY Clockworks S Y 10H 641A Y100H 641A S E M IC O N D U C T O R FE A TU R E S D ES C R IPTIO N I New design - replaces SY10/100H641 The SY10/100H641A are single supply, low skew translating 1:9 clock drivers. Devices in the Synergy

eel -16-2005

Abstract: SY100H842 SY100H842ZC SY10H842 SY10H842ZC
Contextual Info: * SINGLE SUPPLY PECL-TTL 1:4 CLOCK DRIVER SYNERGY SEM IC O N D U C TO R FEATURES • ■ ■ ■ C lockw orks SY10H842 Y100H842 DESCRIPTION Translates positive ECL to TTL PECL-TTL 300ps pin-to-pin skew Guaranteed skew spec Differential Internal design for Increased noise

Contextual Info: A V 3.3V SINGLE SUPPLY QUAD pF r| SYNERGY C lockworks PRELIMINARY SY10H841L Y100H841L T n T T | W |T H PECL-TO-TTL WITH OUTPUT ENABLE S E M IC O N D U C T O R DESCRIPTION FEATURES • 3.3V power supply ■ Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew

d313d

Contextual Info: * REG ISTERED HEX PECL-TO-TTL SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • Differential PECL data and clock inputs ■ 48mA sink, 15mA source TTL outputs ■ Single +5V power supply ■ Multiple power and ground pins to minimize noise ■ Specified within-device skew

Contextual Info: DESCRIPTION FEATURES • ECL/TTL version of popular ECLinPS El 11 ■ 400ps within device skew ■ 800ps part-to-part skew ■ Latch ■ Differential internal design ■ V bb output ■ Dual supply ■ Reset/Enable ■ Multiple TTL and ECL power/ground pins