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    T10103

    Abstract: 74ACT11112
    Contextual Info: 54ACT11112, 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0103—D3339, JUNE 1989— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54 A C T 1 1 1 1 2 . . . J P ACKA G E 7 4 A C T 1 1112 . . . D O R N P ACKA G E


    OCR Scan     		54act1111274act11112ti0103d3339+3500-ma300-milt10103 PDF

    TI0103

    Contextual Info: 54ACT11112, 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0103— D 3339, JUNE 1989— REVISED JAN U AR Y 1990 • Inputs are TTL-Voltage Compatible 54ACT11112 . . . J PACKAGE 74ACT11112 . . . D OR N PACKAGE Flow-Through Architecture to Optimize PCB


    OCR Scan     		54act1111274act11112i0103--500-ma+2300-milti0103 PDF

    TI0103

    Contextual Info: 54ACT11112, 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0 1 0 3 — D 3 3 3 9 • Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout C 1 U 1Q C 2 1 PRE IQ • EPIC'“ Enhanced-Performance Implanted


    OCR Scan     		54act1111274act11112500-ma300-mil+1ti0103 PDF