SI5020 Search Results

S3050 power ic

Abstract: S3050 amcc CDR MAX8875EUK25 MC74VHC1GT04 Si5020 Si5020C-BA s3050-ba
Contextual Info: Si5020C-BA Si5020 M I C R O PCB W I T H S 3 0 5 0 F O O T P R I N T Features ! Supports substitution of the Si5020 in systems designed for AMCC S3050 footprint ! Simplifies evaluation of the Si5020 device ! DSPLL technology eliminates external loop filter components

GR-253-CORE

Abstract: Si5020 Si5020-BM
Contextual Info: Si5020 SiPHY M ULTI -R ATE SONET/SDH C LOCK AND D ATA R ECOVERY IC Features Complete high-speed, low-power, CDR solution includes the following: ! ! ! ! ! Supports OC-48/12/3, STM-16/4/1, ! Gigabit Ethernet, and 2.7 Gbps FEC Low Power—270 mW TYP OC-48 !

Si5020-EVB-10

Abstract: 1729018 AN42 AN43 BLM31A601S MAX6376XR23-T Si5020
Contextual Info: Si 5 0 2 0 - EVB EVALUATION BOARD FOR Si5020 SiPHY MULTI-RATE S O N E T / S D H C L O C K A N D D A TA R E C O V E R Y I C Description Features The Si5020 evaluation board provides a platform for testing and characterizing Silicon Laboratories’ Si5020

Contextual Info: Si5020 SiPHY M ULTI -R ATE SONET/SDH C LOCK AND D ATA R ECOVERY IC Features Complete high-speed, low-power, CDR solution includes the following:      Supports OC-48/12/3, STM-16/4/1,  Gigabit Ethernet, and 2.7 Gbps FEC Low Power—270 mW TYP OC-48 

Si5018-BM

Abstract: Si5018-KM Si5020 Si5020-BM Si5020-KM Si5018
Contextual Info: Si5020 MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC FOR OC-3/12/48, STM 1/4/16, GbE, AND 2.7 Gbps APPLICATIONS FEATURES • Multi-rate operation: OC-3/12/48, STM-1/4/16, Gigabit Ethernet, and 2.7 Gbps FEC • Low power: 300 mW TYP • Small footprint: 20-pin MLP,

Contextual Info: Si5020 SiPHY M ULTI -R ATE SONET/SDH C LOCK AND D ATA R ECOVERY IC Features Complete high-speed, low-power, CDR solution includes the following: Ordering Information: See page 18. Applications Pin Assignments SONET/SDH test equipment „ Optical transceiver modules

QFN 4x4 mm 20L

Abstract: GR-253-CORE Si5010 Si5020 20pin QFN 3x3
Contextual Info: Si5020 SiPHY M ULTI -R ATE SONET/SDH C LOCK AND D ATA R ECOVERY IC Features Complete high-speed, low-power, CDR solution includes the following: „ „ „ „ „ Supports OC-48/12/3, STM-16/4/1, „ Gigabit Ethernet, and 2.7 Gbps FEC Low Power—270 mW TYP OC-48 „

CAL Controls

Abstract: AN42 MAX8875EUK25 Si5010 Si5018 Si5020 Si5310 Si5311 voltage detector IC
Contextual Info: AN42 CONTROLLING DSPLL SELF-CALIBRATION FOR THE S I 5 0 2 0 / 5 0 1 8 / 5 0 1 0 C D R D E V I C E S A N D S I 531 X C L O C K MULTIPLIER/REGENERATOR DEVICES DSPLL™ Self Calibration The Si5020, Si5018, Si5010, Si5310, and Si5311 devices achieve superior jitter performance through the

AN42

Abstract: GR-253-CORE Si5020 ac phase ac 400 v detector 0813S
Contextual Info: Si5020 SiPHY M ULTI -R ATE SONET/SDH C LOCK AND D ATA R ECOVERY IC Features Complete high speed, low power, CDR solution includes the following: ! ! ! ! ! Supports OC-48/12/3, STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC Low Power—270 mW TYP OC-48

Contextual Info: 1CT ! 1CT lOOOpF, 2KV NDTES 1.0 PINS WITHDUT E L E C T R IC A L CDNNECTIDN ARE □MITTED, 2.0 A L L RESISTORS ARE ±5% TOLERANCE, ELECTRICAL SPECIFICATIONS: 1.0 TURNS RATIO: P7-P6-P6-P 8 : (J3— —J 6 (P1 -P3-P 2) : (J1- J2 1CT : 1CT± 3% 1CT : 1CT ± 3%

Contextual Info: 1CT ! 1CT TD SHIELD lOOOpF, 2 K V NDTES 1.0 PINS WITHDUT E L E C T R I C A L CDNNECTIDN ARE DMITTED, 2.0 A L L RESISTORS ARE ± TOLERANCE, ELECTRICAL SPECIFICATIONS: 1 .0 TURNS RATIO: P 7 - P 6 - P 8 (P 1 -P 3 -P 2 ) : (J 3 -J 6 ) : (J 1 -J 2 ) 2 .0 INDUCTANCE:

Si5020

Abstract: Si5100 Si5110 OC-48 STM-16 OC-48 Clock and data recovery
Contextual Info: OC-48 Optical Networking Solutions HIGH PERFORMANCE PHYSICAL LAYER ICS KEY PRODUCTS Si5100/10 Transceivers • Data rates supported: OC-48/STM-16 and 2.7 Gbps FEC • Integrated limiting amplifier, CDR, CMU and Mux/Demux • DSPLL-based CMU with selectable loop

Contextual Info: 1CT i 1CT lOOOpF, 2KV NDTES 1.0 PINS WITHOUT ELECTRICAL CONNECTION ARE OMITTED. 2.0 ALL RESISTORS ARE ±57. TOLERANCE, ELECTRICAL SPECIFICATIONS: 1.0 TURNS RATIO: P 7 - P 6 - P 8 : (J3 -J6 ) ( P 1 - P 3 - P 2 ) : (J1 -J2 ) 1CT 1CT 2.0 INDUCTANCE: 350uH MIN. @ 0.1V, 100KHz, 8mA DC Bias

Contextual Info: 1C T • 1C T TD+ TD- RCT J1 J2 J3 TX- J4 J5 J6 J7 J8 RX- TX+ RX+ lOOOpF, 2 K V NDTEi 1, UNUSED PIN P7 IS DMITTED, ELECTRICAL SPECIFICATIONS: 1 .0 TURNS RATIO: P 4 - P 5 - P 6 (P 3 -P 2 -P 1 ) : (J 3 -J 6 ) : (J 1 -J 2 ) 2 .0 INDUCTANCE : 3 .0 LEAKAGE INDUCTANCE:

Contextual Info: lOOOpFj 2KV SHIELD -aSJUUUL^ 75 -AA/V0 P7 1 ! 1 @ h 75 • A /W TAB UP NDTES 1,0 PINS WITHDUT ELECTRICAL CDNNECTIDN ARE GMITTED, ELECTRICAL SPECIFICATIONS: 1.0 TURNS RATIO: ( P 5 - P 4 - P 3 ) : (J 3 -J 6 ) ( P 8 - P 7 - P 6 ) : (J 1 -J 2 ) 1CT 1CT 2.0

f311 silabs

Abstract: F321 silabs C8051F350DK silabs f321 Si3010-FS C8051F060 C8051F064 C8051F120DK C8051F330DK C8051F040
Contextual Info: Silicon Labs Digi-Key Catalog High Performance Mixed-Signal Microcontrollers Precision Mixed-Signal Microcontrollers Full-Featured MCUs with up to 100 MIPS and 1Msps 16 Bit ADCs The Precision Mixed-Signal microcontroller family combines high-precision analog data converters with a high-throughput 8051 CPU making them

Contextual Info: Si5018 SiPHY OC-48/STM-16 C LOCK AND D ATA R ECOVERY IC W ITH FEC Features Complete high-speed, low-power, CDR solution includes the following:  Supports OC-48 /STM-16 & FEC  Low power—270 mW typ OC-48   Small footprint: 4x4 mm  DSPLL Eliminates external 

AN42

Abstract: Si5310 Si5311 Si5311-BM PLL 2400 MHZ
Contextual Info: S i 5 3 11 P RECISION H IGH -S PEED C LOCK M ULTIPLIER /R EGENERATOR IC Features Complete precision high-speed clock multiplier and regenerator device: 31 1- B M Regenerates a “clean”, jitterattenuated version of input clock DSPLL technology provides

AN42

Abstract: GR-253-CORE Si5010 Si5010-BM Si5020 0317s
Contextual Info: Si5010 OC-12/3, STM-4/1 SONET/SDH C LOCK AND D ATA R ECOVERY IC Features ! ! ! ! Supports OC-12/3, STM-4/1 Low Power, 293 mW TYP OC-12 Small Footprint: 4 mm x 4 mm DSPLL Eliminates External Loop Filter Components 3.3 V Tolerant Control Inputs ! ! ! !

jedec package MO-220 VGGD-1 QFN

Contextual Info: Si5018 SiPHY OC-48/STM-16 C LOCK AND D ATA R ECOVERY IC W ITH FEC Features Complete high-speed, low-power, CDR solution includes the following: Supports OC-48 /STM-16 & FEC „ Low power—270 mW typ OC-48 „ „ Small footprint: 4x4 mm „ DSPLL™ Eliminates external „

Contextual Info: Si5018 SiPHY OC-48/STM-16 C LOCK AND D ATA R ECOVERY IC W ITH FEC Features Complete high-speed, low-power, CDR solution includes the following: „ Supports OC-48 /STM-16 & FEC „ Low power—270 mW „ typ OC-48 „ Small footprint: 4x4 mm „ DSPLL™ Eliminates external „

SI5010

Abstract: AN42 GR-253-CORE Si5010-BM Si5020
Contextual Info: Si5010 OC-12/3, STM-4/1 SONET/SDH C LOCK AND D ATA R ECOVERY IC Features Complete CDR solution includes the following: ! ! ! ! ! Supports OC-12/3, STM-4/1 Low power, 293 mW TYP OC-12 Small footprint: 4 x 4 mm DSPLL eliminates external loop filter components

Si32176

Abstract: si3217 Si32171 SIL F330 Si32178 Si3239 si2167 Si4735 SI3205 Si32177
Contextual Info: PRODUCT SELECTOR GUIDE T0 RAM ROM Expansion Control ALE /PSEN I/O ports P3 P2 P1 P0 T1 Timers Serial Port TxD FA L L 2 010 High-Performance, Analog-Intensive, Mixed-Signal ICs www.silabs.com RxD PRODUCT SELECTOR GUIDE Product Selector Tables GET FULL PRODUCT LISTINGS, DATA SHEETS, APP NOTES, SAMPLES AND MORE AT www.silabs.com

Contextual Info: 1CT i 1CT lOOOpF, 2KV NDTES 1.0 A L L R ESISTO R S ARE ±5 V. TOLERANCE, ELECTRICAL SPECIFICATIONS: 1.0 TURNS RATIO: P 7 - P 6 - P 8 : (J3 -J6 ) ( P 1 - P 3 - P 2 ) : (J1 -J2 ) 1CT 1CT 2.0 INDUCTANCE: 350uH MIN. @ 0.1V, 100KHz, 8mA DC Bias 350uH MIN. @ 0.1V, 100KHz, 8mA DC Bias