ST10R Search Results

Contextual Info: SCS-THOMSON *JM > DSll g|g@ilUl inMID @ ST10R163 16-BIT ROMLESS MICROCONTROLLER DATASHEET High performance 16-bit CPU with 4-stage pipeline 80ns instruction cycle time at 25-MHz CPU clock 400 ns multiplication (16 x 16 bits , 800 ns division (32 /1 6 bit)

Contextual Info: / IT G S-1 H 0 M S0 N #. SIMOtg^lULKgìfMnigg_ ST10R163 16-BIT ROMLESS MICROCONTROLLER D ATASH EET • High performance 16-bit CPU with 4-stage pipeline ■ 80ns instruction cycle time at 25-MHz CPU clock ■ 400 ns multiplication 16 x 16 bits , 800 ns

ST10

Abstract: ST10R172L st10 Bootstrap
Contextual Info: ST10R172L 16-BIT LOW VOLTAGE ROMLESS MCU DATASHEET • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ■ ● ● ● ● ● OSC WDT Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus Multiplexed or demultiplexed external

ST10

Abstract: ST10F166 ST10R165 st10 Bootstrap
Contextual Info: ST10R165 16-BIT MCU USER MANUAL MARCH 1995 INTRODUCTION The rapidly growing area of embedded control applications is representing one of the most time-critical operating environments for today’s microcontrollers. Complex control algorithms have to be processed based on a large number

ST10

Abstract: ST10R165 T4836 st10 Bootstrap
Contextual Info: ST10R165 16-BIT ROMLESS MICROCONTROLLER DATASHEET • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ June 1997 Internal Ram Watchdog PEC Interrupt C ontroller 16 16 16 8 Port 6 GPT1 GPT2 Port 5 8 SSC ■ 16 16 ASC USART ■ CPU-Core

ST10

Abstract: ST10R172L st10 Bootstrap
Contextual Info: ST10R172L 16-BIT LOW VOLTAGE ROMLESS MCU PRODUCT PREVIEW • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ■ ● ● ● ● ● OSC WDT Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus

BR03

Abstract: ST10R172L ST10R172L-B0
Contextual Info: ST10R172L-B0 16-BIT LOW VOLTAGE ROMLESS MCU ERRATA SHEET 1 INTRODUCTION This errata sheet describes the functional problems known in the step B0 of the ST10R172L-B0. This is the erratasheet of the ST10R172L datasheet version 1.2 of March 2001. 2 FUNCTIONAL PROBLEMS

BCD 7SEGMENT

Abstract: digital clock with 7segment BCD to 7segment decoder 7SEGMENT 5 T523H 7segment all stk ic diagram c166 C programming PEC 302 PRESET 1MOHMS
Contextual Info: ST10R272L USER’S MANUAL Release 1.0 Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Contextual Info: ST10R167 16-BIT ROMLESS MCU • 16 32 ROMLESS 16 Internal RAM 16 CPU-Core PEC Watchdog 16 XRAM Interrupt Controller 16 OSC. 8 Port 6 8 Port 5 16 BRG BRG Port 3 15 Port 7 8 August 1999 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

MCW D15

Abstract: ST10 TQFP-100 T11C
Contextual Info: ST10R262 16-BIT MCU WITH ON-CHIP MAC PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ High Performance CPU ■ Multiply-Accumulate unit MAC ■ 16-bit CPU with 4-stage pipeline and 40ns instruction cycle time at 50-MHz CPU clock ■ Register-based architecture

Contextual Info: SGS-THOMSON ST10R 165 iM ig ia o iiU K g T r M n 16-BIT ROMLESS MICROCONTROLLER PRELIMINARY DATA High performance 16-bit CPU with 4-stage pipeline 100 nsinstruction cycle timeat20-MHz CPU clock 500 ns multiplication 16 x 16 bits , 1 jos division (32/16 bit)

ST10R272L-B0

Abstract: ST10R272L BR03 ST10 saturation instructions
Contextual Info: ST10R272L-B0 16-BIT ROMLESS LOW VOLTAGE MCU WITH MAC ERRATA SHEET 1 INTRODUCTION This errata sheet describes the functional and electrical problems known in the step B0 of the ST10R272L-B0. This is the erratasheet of the ST10R272L datasheet version 1.2 of april

st10 Bootstrap

Abstract: ST10R272L
Contextual Info: ST10R272L 16-BIT LOW VOLTAGE ROMLESS MCU WITH MAC PRODUCT PREVIEW • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ● ■ CPU Frequency: 0 to 50 MHz 40ns instruction cycle time at 50-MHz CPU clock Multiply-Accumulate unit MAC 4-stage pipeline

BR03

Abstract: ST10R172L ST10R172L-B0
Contextual Info: ST10R172L-B0  16-BIT LOW VOLTAGE ROMLESS MCU ERRATA SHEET 1 INTRODUCTION This errata sheet describes the functional problems known in the step B0 of the ST10R172L-B0. This is the erratasheet of the ST10R172L datasheet version 1.1 of april 2000. 2 FUNCTIONAL PROBLEMS

ST10R272L

Abstract: BR03 ST10 ST10R272L-B0 ST10 FAMILY PROGRAMMING MANUAL
Contextual Info: ST10R272L-B0 16-BIT ROMLESS LOW VOLTAGE MCU WITH MAC ERRATA SHEET 1 INTRODUCTION This errata sheet describes the functional and electrical problems known in the step B0 of the ST10R272L-B0. This is the erratasheet of the ST10R272L datasheet version 1.3 of March

st10 Bootstrap

Abstract: "saturation arithmetic" ST10R272L
Contextual Info: ST10R272L 16-BIT LOW VOLTAGE ROMLESS MCU WITH MAC PRODUCT PREVIEW • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ● ■ CPU Frequency: 0 to 50 MHz 40ns instruction cycle time at 50-MHz CPU clock Multiply-Accumulate unit MAC 4-stage pipeline

0516H

Abstract: 156Mbit ST10R172L sspc st10 Bootstrap FF12H DPRAM
Contextual Info: ST10R172L 16-BIT LOW VOLTAGE ROMLESS MCU PRODUCT PREVIEW • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ■ ● ● ● ● ● OSC WDT Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus

ST10

Abstract: ST10R165 ST10R165BQ1 st10 Bootstrap ST10 FAMILY PROGRAMMING MANUAL
Contextual Info: ST10R165BQ1 16-BIT ROMLESS MICROCONTROLLER DATASHEET • ■ ■ ■ ■ ■ October 1997 The information in this datasheet is subject to change OSC CPU-Core Internal Ram 16 16 16 Watchdog PEC Interrupt C ontroller Port 6 ■ ■ ■ ■ 6 SSC GPT2 Port 5

lm t83

Abstract: ST10R272L ST10 st10 Bootstrap ST10 PROGRAMMING C basic
Contextual Info: ST10R272L 16-BIT LOW VOLTAGE ROMLESS MCU WITH MAC DATASHEET • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ● ■ ● OSC WDT P.4 P.1 P.0 XSSP ST10 CORE DPRAM MAC Interrupt Controller & PEC ASC GPT1/2 P.3 1KByte on-chip RAM Up to 16 MBytes linear address space for

sft 317 - to1

Abstract: cj cl a17 BH P58 76115 PQFP144 ST10 ST10R167 st10r167 buscon st10 Bootstrap disassembler
Contextual Info: ST10R167 16-BIT ROMLESS MCU • HIGH PERFORMANCE CPU - 16-BIT CPU WITH 4-STAG E PIPELINE - 80ns INSTRUCTION CYCLE TIME @ 25MHz CLK - 400ns 1 6 X 1 6-BIT MULTIPLICATION -8 0 0 n s 3 2 / 16-BIT DIVISION -E N H A N C E D FACILITIES BOOLEAN BIT MANIPULATION -A D D IT IO N A L INSTRUCTIONS TO SU PPO R T HLL

ST10R163

Abstract: st10 Bootstrap
Contextual Info: ST10R163 16-BIT MCU USER MANUAL FEBRUARY 1996 1 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHO UT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics.

T523H

Abstract: lm 1723 cp equivalent digital clock with 7segment Ir sensor ciruit PRESET 1MOHMS ST10X167 C166 ST10 ST10R272L StK 412 230
Contextual Info: ST10R272L USER’S MANUAL Release 1.0  Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ST10R272L

Abstract: ST10 st10 Bootstrap t60T
Contextual Info: ST10R272L 16-BIT LOW VOLTAGE ROMLESS MCU WITH MAC PRODUCT PREVIEW • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ● ■ ● OSC WDT P.4 P.1 P.0 XSSP ST10 CORE DPRAM MAC Interrupt Controller & PEC ASC GPT1/2 P.3 1KByte on-chip RAM Up to 16 MBytes linear address space for

st10 Bootstrap

Contextual Info: ST10R172L 16-BIT LOW VOLTAGE ROMLESS MCU DATASHEET • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ■ ● ● ● ● ● OSC WDT Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus Multiplexed or demultiplexed external