SN74LVC1G00 Search Results

A115-A

Abstract: C101 SN74LVC1G00
Contextual Info: SN74LVC1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCES212R – APRIL 1999 – REVISED SEPTEMBER 2003 D D D D D D D D D Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.8 ns at 3.3 V

Contextual Info: SN74LVC1G00 www.ti.com SCES212V – APRIL 1999 – REVISED FEBRUARY 2010 SINGLE 2-INPUT POSITIVE-NAND GATE Check for Samples: SN74LVC1G00 FEATURES 1 • Available in the Texas Instruments NanoStar Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC1G00 SCES212W – APRIL 1999 – REVISED MARCH 2011 www.ti.com SINGLE 2-INPUT POSITIVE-NAND GATE Check for Samples: SN74LVC1G00 FEATURES 1 • • • • • • • Available in the Texas Instruments NanoStar Package Supports 5-V VCC Operation

A115-A

Abstract: C101 SN74LVC1G00
Contextual Info: SN74LVC1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCES212P – APRIL 1999 – REVISED FEBRUARY 2003 D D D D D D D D D Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.8 ns at 3.3 V

A115-A

Abstract: C101 SN74LVC1G00
Contextual Info: SN74LVC1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCES212R – APRIL 1999 – REVISED SEPTEMBER 2003 D D D D D D D D D Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.8 ns at 3.3 V

Contextual Info: SN74LVC1G00A SINGLE 2-INPUT POSITIVE-NAND GATE SCAS609 – JUNE 1998 D EPIC Enhanced-Performance Implanted D D D D DBV OR DCK PACKAGE (TOP VIEW CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN74LVC1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCES212K – APRIL 1999 – REVISED JUNE 2002 D D D D D D D D Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Typical VOLP Output Ground Bounce

Contextual Info: SN74LVC1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCES212J – APRIL 1999 – REVISED MAY 2002 D D D D D D D D Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Typical VOLP Output Ground Bounce

c00f

Abstract: C005 sot23 pack marking CA5
Contextual Info: SN74LVC1G00 www.ti.com SCES212X – APRIL 1999 – REVISED NOVEMBER 2012 SINGLE 2-INPUT POSITIVE-NAND GATE Check for Samples: SN74LVC1G00 FEATURES 1 • 2 • • • • • • Available in the Texas Instruments NanoStar Package Supports 5-V VCC Operation

A115-A

Abstract: C101
Contextual Info: SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450A – DECEMBER 2003 – REVISED NOVEMBER 2005 FEATURES • • • • • • • 1 • • • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 FEATURES • • • • • • • • • 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: SN74LVC1G00 www.ti.com SCES212Z – APRIL 1999 – REVISED SEPTEMBER 2013 Single 2-Input Positive-NAND Gate Check for Samples: SN74LVC1G00 FEATURES DESCRIPTION • This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation. 1 2 •

Contextual Info: SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 FEATURES • • • • • • • • • 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: SN74LVC1G00 SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES212U – APRIL 1999 – REVISED JANUARY 2007 FEATURES • • • • • • • Available in the Texas Instruments NanoFree Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

Contextual Info: Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN74LVC1G00 SCES212AB – APRIL 1999 – REVISED APRIL 2014 SN74LVC1G00 Single 2-Input Positive-NAND Gate 1 Features • 1 • • • • • • • • • 3 Description

Contextual Info: SN74LVC1G00 SINGLE 2ĆINPUT POSITIVEĆNAND GATE SCES212T − APRIL 1999 − REVISED JUNE 2005 D Available in the Texas Instruments D D D D D D Ioff Supports Partial-Power-Down Mode NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 FEATURES • • • • • • • • • 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450A – DECEMBER 2003 – REVISED NOVEMBER 2005 FEATURES • • • • • • • 1 • • • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450A – DECEMBER 2003 – REVISED NOVEMBER 2005 FEATURES • • • • • • • 1 • • • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: SN74LVC1G00 SINGLE 2ĆINPUT POSITIVEĆNAND GATE SCES212T − APRIL 1999 − REVISED JUNE 2005 D Available in the Texas Instruments D D D D D D Ioff Supports Partial-Power-Down Mode NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC1G00 SINGLE 2ĆINPUT POSITIVEĆNAND GATE SCES212T − APRIL 1999 − REVISED JUNE 2005 D Available in the Texas Instruments D D D D D D Ioff Supports Partial-Power-Down Mode NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

SN74LVC1G00

Contextual Info: SN74LVC1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCES212B – APRIL 1999 – REVISED FEBRUARY 2000 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process Ioff Feature Supports Partial-Power-Down Mode Operation Supports 5-V VCC Operation Package Options Include Plastic

Contextual Info: SN74LVC1G00A SINGLE 2-INPUT POSITIVE-NAND GATE SC AS609 - JU NE 1998 • EPIC Enhanced-Performance Implanted CMOS Subm icron Process • Typical V q lp (O utput Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C • Typical Vq hv DBV OR DCK PACKAGE (TOP VIEW)

c00f

Abstract: MARKING c00 SOT23 marking CA5 marking code CAF
Contextual Info: SN74LVC1G00 www.ti.com SCES212X – APRIL 1999 – REVISED NOVEMBER 2012 SINGLE 2-INPUT POSITIVE-NAND GATE Check for Samples: SN74LVC1G00 FEATURES 1 • 2 • • • • • • Available in the Texas Instruments NanoStar Package Supports 5-V VCC Operation