SN74LV32A Search Results

Contextual Info: SN74LV32AĆEP QUADRUPLE 2ĆINPUT POSITIVEĆOR GATE SCLS565A − JANUARY 2004 − REVISED MAY 2004 D Controlled Baseline D D D D D D D Typical VOLP Output Ground Bounce − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 105°C

SN54LV32A

Abstract: SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385C – SEPTEMBER 1997 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

LV32A

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385E – SEPTEMBER 1997 – REVISED AUGUST 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y

A115-A

Abstract: C101 SN54LV32A SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN74LV32AĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATE SCLS516C − JULY 2003 − REVISED FEBRUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y

SN74LV32A

Abstract: SN74LV32A-Q1 SN74LV32ATPWRG4Q1 SN74LV32ATPWRQ1
Contextual Info: SN74LV32A-Q1 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCLS516C − JULY 2003 − REVISED FEBRUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D Ioff Supports Partial-Power-Down Mode D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 11

A115-A

Abstract: C101 SN54LV32A SN74LV32A 74LV32a
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

A115-A

Abstract: C101 SN54LV32A SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

A115-A

Abstract: C101 SN54LV32A SN74LV32A 74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385D – SEPTEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES S C L S 3 8 5 A - S E P TE M B E R 1997 - R EVISED A P R IL 1998 EP/C Enhanced-Performance Implanted CMOS Process SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)

Contextual Info: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C

LV32

Contextual Info: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C

Contextual Info: SN74LV32A-Q1 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCLS516C − JULY 2003 − REVISED FEBRUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74LV32AĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS516B − JULY 2003 − REVISED MAY 2004 D Qualification in Accordance With D D D D D D D D Supports Mixed-Mode Voltage Operation on AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control

A115-A

Abstract: C101 SN54LV32A SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C

SN54LV32A

Abstract: SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385B – SEPTEMBER 1997 – REVISED NOVEMBER 1999 D D D D D EPIC Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y