SN74ACT10 Search Results

A115-A

Abstract: SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 D Designed to Ensure Defined Voltage Levels D D D D D D D D DW OR NS PACKAGE TOP VIEW on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

R-PDSO-G* Package

Abstract: A115-A SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

SN54ACT10

Abstract: SN74ACT10 SN74ACT10D SN74ACT10DBR SN74ACT10DR SN74ACT10N SN74ACT10NSR SN74ACT10PW SN74ACT10PWR
Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS526C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 9.5 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT10 . . . FK PACKAGE

SN74ACT1071

Abstract: SN74ACT1071D SN74ACT1071DE4 SN74ACT1071DG4 SN74ACT1071DR SN74ACT1071DRE4
Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

csf TEXAS

Abstract: DJD4322 SN54ACT10 SN74 SN74ACT10 CSF165
Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS526 - AUGUST 1995 Inputs Are TTL-Voltage Compatible EPIC Enhanced-Performance Implanted CMOS 1-jxm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW)

SN74ACT1071

Abstract: d3994
Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

SN74ACT1071

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 DW OR NS PACKAGE TOP VIEW D Designed to Ensure Defined Voltage Levels D D D D D D D D on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

SN54ACT10

Abstract: SN74ACT10 SN74ACT10D SN74ACT10DBR SN74ACT10DR SN74ACT10N SN74ACT10NSR SN74ACT10PW SN74ACT10PWR
Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS526C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 9.5 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT10 . . . FK PACKAGE

SN54ACT10

Abstract: SN74ACT10
Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS526A – AUGUST 1995 – REVISED APRIL 1996 D D D SN54ACT10 . . . J OR W PACKAGE SN74ACT10 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

SN54ACT10

Abstract: SN74ACT10 SN74ACT10D SN74ACT10DBR SN74ACT10DR SN74ACT10N SN74ACT10NSR SN74ACT10PW SN74ACT10PWR
Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS526C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 9.5 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT10 . . . FK PACKAGE

Contextual Info: SN74ACT10ĆQ1 TRIPLE 3ĆINPUT POSITIVEĆNAND GATE SCAS784 – OCTOBER 2004 D Qualification in Accordance With D OR PW PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D D 1A 1B 2A 2B 2C 2Y

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

A115-A

Abstract: SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

Contextual Info: SN74ACT10ĆQ1 TRIPLE 3ĆINPUT POSITIVEĆNAND GATE SCAS784A – OCTOBER 2004 − REVISED JANUARY 2008 D D D D D D OR PW PACKAGE TOP VIEW Qualified for Automotive Applications 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 9.5 ns at 5 V

SN54ACT10

Abstract: SN74ACT10 SN74ACT10D SN74ACT10DBR SN74ACT10DR SN74ACT10N SN74ACT10NSR SN74ACT10PW SN74ACT10PWR
Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS526C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 9.5 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT10 . . . FK PACKAGE

Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS526C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 9.5 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT10 . . . FK PACKAGE

Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS526A – AUGUST 1995 – REVISED APRIL 1996 D D D SN54ACT10 . . . J OR W PACKAGE SN74ACT10 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS526C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 9.5 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT10 . . . FK PACKAGE

Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS526C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 9.5 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT10 . . . FK PACKAGE

Contextual Info: SN74ACT1073NSR IL08 C-MOS 16-BIT BUS-TERMINATION ARRAY —TOP VIEW— 15 1 D1 1 20 D16 2 3 D2 2 19 D15 4 7 D3 3 18 D14 8 9 D4 4 17 D13 10 11 5 GND VDD 16 12 13 6 GND VDD 15 14 17 D5 7 14 D12 18 19 D6 8 13 D11 D7 9 12 D10 D8 10 11 D9 D1 VDD VDD 1 16 15 TG GND

SN74ACT1073

Abstract: SCAS193
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193 – D3992, MARCH 1992 – REVISED APRIL 1993 • • • • • • • DW PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot