SCLS182 Search Results

SN54LV00

Abstract: SN74LV00 SN74LV00D SN74LV00DBLE SN74LV00DR SN74LV00PWLE
Contextual Info: SN54LV00, SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

SN74LV00

Abstract: SN54LV00
Contextual Info: SN54LV00, SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

SN54LV00

Abstract: SN74LV00
Contextual Info: SN54LV00, SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

SN54LV00

Abstract: SN74LV00 SN74LV00D SN74LV00DBLE SN74LV00DR SN74LV00PWLE
Contextual Info: SN54LV00, SN74LV00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS182C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y SN54LV00 . . . FK PACKAGE

SN74ALVCH162245

Abstract: Schottky Barrier Diode Bus-Termination Array SN7400 CLOCKED SLLS210 SCAD001D TEXAS INSTRUMENTS SN7400 SERIES buffer SN74LVCC4245 sn74154 SDAD001C SN7497
Contextual Info: Section 4 Logic Selection Guide ABT – Advanced BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

SN74HC02 Spice model

Abstract: philips semiconductor data handbook SDAD001C SDFD001B SCAD001D SN7497 spice model SN74AHC14 spice Transistor Crossreference SLLS210 ci ttl sn74ls00
Contextual Info: LOGIC OVERVIEW 1 FUNCTIONAL INDEX 2 FUNCTIONAL CROSSĆREFERENCE 3 DEVICE SELECTION GUIDE 4 3 LOGIC SELECTION GUIDE FIRST QUARTER 1997 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

SN74LV00

Abstract: 122A-4
Contextual Info: SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS1S2A- FEBRUARY 1993-REVISED JULY 1995 • EPIC Enhanced-Performance Implanted CMOS 2-n Process • Typical Volp (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C • Typical Vohv (Output V q h Undershoot)

Contextual Info: SN54LV00, SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES _ S C L S 1B 2C -F E B R U A R Y 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V(j|_p (Output Ground Bounce)« 0.8 V at Vcc> TA = 25°C

SN74LV00

Contextual Info: SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS182 - F E B R U A R Y 1993 - REVISED M ARCH 1994 » EPIC Enhanced-Performance Implanted CMOS 2-(i Process D, D B, O R P W P A C K A G E (TO P VIEW) • Typical V q l p (Output Ground Bounce)