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SCAS792 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
SB866 Contextual Info: SN74SSTUB32866 www.ti.com SCAS792 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792 25-BIT 14-Bit SN74SSTUB32866 SB866	PDF
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit SN74SSTUB32866	PDF
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit SN74SSTUB32866	PDF
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit SN74SSTUB32866	PDF
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit	PDF
Q11A Abstract: SB866 SN74SSTUB32866 SN74SSTUB32866ZKER SN74SSTUB32866ZWLR D8-D13 D8-D10 Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit Q11A SB866 SN74SSTUB32866 SN74SSTUB32866ZKER SN74SSTUB32866ZWLR D8-D13 D8-D10	PDF
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792A – OCTOBER 2006 – REVISED AUGUST 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTUB32866 SCAS792A 25-BIT 14-Bit SN74SSTUB32866	PDF
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit SN74SSTUB32866	PDF
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit SN74SSTUB32866	PDF
D8-D13 Abstract: Q11A Q13A SB866 SN74SSTUB32866 SN74SSTUB32866ZKER Contextual Info: SN74SSTUB32866 www.ti.com SCAS792 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792 25-BIT 14-Bit D8-D13 Q11A Q13A SB866 SN74SSTUB32866 SN74SSTUB32866ZKER	PDF
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit SN74SSTUB32866	PDF
SB866 Abstract: D8-D13 Q11A SN74SSTUB32866 SN74SSTUB32866ZKER SN74SSTUB32866ZWLR Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit SB866 D8-D13 Q11A SN74SSTUB32866 SN74SSTUB32866ZKER SN74SSTUB32866ZWLR	PDF
Contextual Info: SN74SSTUB32866 w w w .t i.c om SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit	PDF
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2	Original	SN74SSTUB32866 SCAS792C 25-BIT 14-Bit SN74SSTUB32866	PDF

SB865A Abstract: SB866A ddr2 PLL JESD82 SSTUx32864 SSTU32868 JEDEC DDR2-400 2rx8 SB866 SN74SSTUB32866 Contextual Info: Application Report SCAA101 – March 2009 DDR2 Memory Interface Clocks and Registers – Overview Christian Schmoeller . CDC - Clock Distribution Circuits ABSTRACT This application report gives an overview of the existing JEDEC DDR2 Register and	Original	SCAA101 SB865A SB866A ddr2 PLL JESD82 SSTUx32864 SSTU32868 JEDEC DDR2-400 2rx8 SB866 SN74SSTUB32866	PDF