SCAS587B Search Results

SCAS587B Equivalents

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SCAS587B Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CDC318 Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin CDC318	PDF
TL 650 ht Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH \|2C CONTROL INTERFACE SCAS587B - JANUARY 1997 - REVISED MARCH 1998 High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM SDRAM Clock Buffering Applications Output Skew, tSk(0), Less Than 250 ps Pulse Skew, tSk(P), Less Than 650 ps	OCR Scan	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin TL 650 ht	PDF
Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin	PDF
CDC318 Abstract: CDC318DL CDC318DLR Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin CDC318 CDC318DL CDC318DLR	PDF
CDC318 Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin CDC318	PDF
Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin	PDF