SCAS587B Search Results
SCAS587B Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
CDC318Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps |
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cdc31818-linescas587b1-to-18+2 | |
TL 650 htContextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH |2C CONTROL INTERFACE SCAS587B - JANUARY 1997 - REVISED MARCH 1998 High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM SDRAM Clock Buffering Applications Output Skew, tSk(0), Less Than 250 ps Pulse Skew, tSk(P), Less Than 650 ps |
OCR Scan |
cdc31818-linescas587b1-to-18+3 | |
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Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps |
Original |
cdc31818-linescas587b1-to-18+2 | |
CDC318
Abstract: CDC318DL CDC318DLR
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Original |
cdc31818-linescas587b1-to-18+4 | |
CDC318Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps |
Original |
cdc31818-linescas587b1-to-18+2 | |
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Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps |
Original |
cdc31818-linescas587b1-to-18+2 |