SCAS19 Search Results

A115-A

Abstract: SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 D Designed to Ensure Defined Voltage Levels D D D D D D D D DW OR NS PACKAGE TOP VIEW on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

SN74ACT7803

Abstract: SN74ACT7805 SN74ACT7813
Contextual Info: SN74ACT7803 512 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS191 - MARCH 1991 - REVISED MARCH 1992 DL PACKAGE TOP VIEW • Member of the Texas Instruments W id e b u s F a m ily • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident U 56

R-PDSO-G* Package

Abstract: A115-A SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

SN74ACT1071

Abstract: SN74ACT1071D SN74ACT1071DE4 SN74ACT1071DG4 SN74ACT1071DR SN74ACT1071DRE4
Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

74ACT16475

Abstract: 54ACT16475
Contextual Info: 54ACT16475, 74ACT16475 18-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS198A – OCTOBER 1990 – REVISED APRIL 1996 D D D D D D D D Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Inverting Outputs Flow-Through Architecture Optimizes

SN74ACT1071

Abstract: d3994
Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

SN74ACT8994

Abstract: PIN CONFIGURATION pci 32 bit 5 v
Contextual Info: SN74ACT8994 DIGITAL BUS MONITOR IEEE STD 1149.1 JTAG SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER SCAS196E – JULY 1990 – REVISED DECEMBER 1996 D D D D D D D Member of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard

JW333

Abstract: lm 7803
Contextual Info: SN74ACT7803 512 x 1 8 C L O C K E D FIRST-IN, FI RS T - OU T M E M O R Y SCAS191A - MARCH 1991 - REVISED JULY 1995 DL PACKAGE I TOP VIEW I 1 1 • M e m b e r o f the Texas I n s t r u m e n t s W i d e b u s F ami ly I I • F re e - R un n i n g Read and Wr i te C l o c k s Can

SN74ACT1071

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 DW OR NS PACKAGE TOP VIEW D Designed to Ensure Defined Voltage Levels D D D D D D D D on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

Contextual Info: 74AC11590 8ĆBIT BINARY COUNTER WITH REGISTERED 3ĆSTATE OUTPUTS ą SCAS194 − D3988, MARCH 1992 − REVISED APRIL 1993 • • • • • • • DW OR N PACKAGE TOP VIEW Parallel Registered Outputs Internal Counters Have Direct Clear Flow-Through Architecture Optimizes

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

74ACT16475

Contextual Info: 54ACT16475, 74ACT16475 18-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS198A – OCTOBER 1990 – REVISED APRIL 1996 D D D D D D D D Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Inverting Outputs Flow-Through Architecture Optimizes

Contextual Info: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199B – JANUARY 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized

74AC11590

Contextual Info: 74AC11590 8-BIT BINARY COUNTER WITH REGISTERED 3-STATE OUTPUTS SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993 • • • • • • • DW OR N PACKAGE TOP VIEW Parallel Registered Outputs Internal Counters Have Direct Clear Flow-Through Architecture Optimizes

Contextual Info: 74ACT11590 8ĆBIT BINARY COUNTER WITH REGISTERED 3ĆSTATE OUTPUTS ą SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993 • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Parallel Registered Outputs Internal Counters Have Direct Clear

ACT8990

Abstract: SN54ACT8990 SN74ACT8990
Contextual Info: SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES SCAS190E – JUNE 1990 – REVISED JANUARY 1997 D D D D D Members of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard

act7813

Contextual Info: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199B – JANUARY 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized

Contextual Info: SN74ACT7803 512 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS191C – MARCH 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

w65 transistor

Abstract: SN74ACT7803 SN74ACT7805 SN74ACT7813
Contextual Info: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199 – JANUARY 1991 – REVISED APRIL 1992 • • • • • • • • • • • • • Member of the Texas Instruments Widebus  Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident

A115-A

Abstract: SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

Contextual Info: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199B – JANUARY 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized

Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation