SCAS01 Search Results

Contextual Info: 74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS013C – AUGUST 1987 – REVISED APRIL 1996 D D D, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted

Contextual Info: 74AC11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS010B – JULY 1987 – REVISED APRIL 1996 D D D D D D DB, DW, NT, OR PW PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: 54ACT11533, 74ACT11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS ą SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • • • • Eight Latches in a Single Package 3-State Bus-Driving Inverting Outputs Full Parallel Access for Loading

D2957

Abstract: 54ACT11533 74ACT11533 ACT11373
Contextual Info: 54ACT11533, 74ACT11533 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS017A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • • • • • • • Eight Latches in a Single Package 3-State Bus-Driving Inverting Outputs Full Parallel Access for Loading

Contextual Info: 74AC11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS01 OB - JULY 1987 - REVISED APRIL 1996 3-State Outputs Drive Bus Lines Directly DB, DW, NT, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout A1 [ 1 Center-Pin V^c and GND Configurations

Contextual Info: 74ACT11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS015B - JUNE 1987 - REVISED APRIL 1996 DB, DW, OR NT PACKAGE TOP VIEW • Eight Latches in a Single Package • 3-State Bus Driving True O utputs • Full Parallel Access fo r Loading •

54AC11027

Abstract: 74AC11027
Contextual Info: 54AC11027, 74AC11027 TRIPLE 3-INPUT POSITIVE-NOR GATES SCAS019A – JULY 1987 – REVISED APRIL 1993 • 54AC11027 . . . J PACKAGE 74AC11027 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: 54ACT11241, 74ACT11241 OCTAL BUFFERS/LINE DRIVERS WITH 3ĆSTATE OUTPUTS ą SCAS011B − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • 54ACT11241 . . . JT PACKAGE 74ACT11241 . . . DB, DW OR NT PACKAGE 3-State Outputs Drive Bus Lines or Buffer

Contextual Info: 54ACT11021, 74ACT11021 DUAL 4ĆINPUT POSITIVEĆAND GATES ą ą SCAS012B − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • 54ACT11021 . . . J PACKAGE 74ACT11021 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes

74ACT11008

Contextual Info: 74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS013C - AUGUST 1987 - REVISED APRIL 1996 Inputs Are TTL-Voltage Compatible Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Performance Implanted CMOS 1-ii.m Process

Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A - D2957, JUNE 1987 - REVISED APRIL 1993 • * Inputs Are TTL-Voltage Compatible ■ ■ * Flow-Through Architecture to Optimize PCB Layout I I * Center-Pin V^c and GND Configurations to Minimize High-Speed Switching Noise

Contextual Info: 54ACT11241, 74ACT11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS011B - D2957, JULY 1987 - REVISED APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 54ACT11241 . . . JT PACKAGE 74ACT11241 . . . DB, DW OR NT PACKAGE 1

Contextual Info: 74AC11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS010B – JULY 1987 – REVISED APRIL 1996 D D D D D D DB, DW, NT, OR PW PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

54ACT11010

Abstract: 74ACT11010 D2957
Contextual Info: 54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: 74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS014C – AUGUST 1987 – REVISED APRIL 1996 D D D D D D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

74ACT11008

Abstract: 74ACT11008D 74ACT11008DR 74ACT11008N 74ACT11008NSR 74ACT11008PW 74ACT11008PWLE 74ACT11008PWR MTSS001C
Contextual Info: 74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS013C – AUGUST 1987 – REVISED APRIL 1996 D D D, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted

54AC11245

Abstract: 74AC11244 74AC11245 1L1723
Contextual Info: 54AC11245, 74AC11245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS01OA - JULY 1987 - R E V IS E D APRIL 1993 • 3-State Outputs Drive Bus Lines Directly 54AC11245 . . . JT PACKAGE 74AC11244 . . . DB, DW, NT, OR PW PACKAGE • Flow-Through Architecture Optimizes

74ACT11373DW

Abstract: 74ACT11373DWE4 74ACT11373DWG4 74ACT11373DWR 74ACT11373 74ACT11373DBLE 74ACT11373DBR 74ACT11373DBRE4 74ACT11373DBRG4
Contextual Info: 74ACT11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS015B – JUNE 1987 – REVISED APRIL 1996 D D D D D D D D D D DB, DW, OR NT PACKAGE TOP VIEW Eight Latches in a Single Package 3-State Bus Driving True Outputs Full Parallel Access for Loading

74ACT11373

Abstract: 74ACT11373DBLE 74ACT11373DBR 74ACT11373DBRE4 74ACT11373DW 74ACT11373DWE4 74ACT11373DWR 74ACT11373DWRE4 74ACT11373NSR
Contextual Info: 74ACT11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS015B – JUNE 1987 – REVISED APRIL 1996 D D D D D D D D D D DB, DW, OR NT PACKAGE TOP VIEW Eight Latches in a Single Package 3-State Bus Driving True Outputs Full Parallel Access for Loading

74AC11008D

Abstract: 74AC11008 74AC11008DE4 74AC11008DR 74AC11008DRE4 74AC11008N 74AC11008NE4 74AC11008PWLE 74AC11008PWR
Contextual Info: 74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS014C – AUGUST 1987 – REVISED APRIL 1996 D D D D D D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

74ACT11008NSRE4

Abstract: 74ACT11008 74ACT11008D 74ACT11008DE4 74ACT11008DR 74ACT11008DRE4 74ACT11008N 74ACT11008NE4 74ACT11008NSR
Contextual Info: 74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS013C – AUGUST 1987 – REVISED APRIL 1996 D D D, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted

Contextual Info: 74AC11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS010B – JULY 1987 – REVISED APRIL 1996 D D D D D D DB, DW, NT, OR PW PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: 74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS014C – AUGUST 1987 – REVISED APRIL 1996 D D D D D D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: 54ACT11533, 74ACT11533 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS017A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • • • • • • • Eight Latches in a Single Package 3-State Bus-Driving Inverting Outputs Full Parallel Access for Loading