RM5231 Search Results

ACT5231

Abstract: ACT-5231PC-133F22C R4700 R5000 RM5231
Contextual Info: ACT5231 32-Bit Superscaler Microprocessor Features • Full militarized QED RM5231 microprocessor ■ Pinout compatible with popular RM5230 with split power sup plies 2.5V and 3.3V ■ Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle

LIC AGENTS DATA

Abstract: RM5231A R4000 RM5200 lic policy
Contextual Info: :15 :32 AM RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary Th ur sd ay ,0 8A ug us t, 2 00 2 06 RM5231A Data Sheet Proprietary and Confidential Preliminary Issue 3, February 2002 Do wn loa de db yt am er na bil of Si lic on Ex pe rt

MIPS RM5231

Abstract: RM5231-150Q R4000 R4650 R4700 R5000 RM5231
Contextual Info: RM5231 Superscalar Microprocessor with 64-Bit System Bus FEATURES • Dual Issue superscalar microprocessor — 150, 200, 225, & 250 MHz operating frequencies — 300 Dhrystone2.1 MIPS — SPECInt95 5.0, SPECfp95 5.25 • System interface optimized for embedded applications

5650300

Abstract: XXXW
Contextual Info: QED RISCMark RM5231™ 64-Bit Superscalar Microprocessor FEATURES: • Pinout com p atib le w ith po pu lar R M 5230 w ith split po w e r s u p ­ plies 2.5V and 3.3V • Dual Issue su p e rsca la r m icro p ro ce sso r - can issue one integer and one floa ting -point in stru ction pe r cycle

hurricane

Abstract: V320USC EVALUATION KIT HR52312003220 pci slot pcb layout MH64BT0330011 RM5231 V320USC pci card schematic V320USC-75LP
Contextual Info: Hurricane V320USC EVALUATION KIT with the QED RM5231 MIPS® Processor Features the V320USC PCI System Controller for 32-bit PCI Bus, designed by V3 Semiconductor Supports QED® RM5230™ and RM5231™ processors Fully compliant with PCI Local Bus Specification, Revision 2.2

Contextual Info: 07 :2 1: 44 P M RM5231A Microprocessor with 32-Bit System Bus Data Sheet Released co n Tu es da y, 24 Ja nu ar y, 20 12 RM5231A Data Sheet Proprietary and Confidential Released Issue 4, February 2004 Do wn lo a de d [c on tro lle d] by Co n te nt Te am

Contextual Info: :5 1: 53 AM RM5231A Microprocessor with 32-Bit System Bus Data Sheet Released Tu es da y, 03 Au g us t, 20 04 10 RM5231A Data Sheet Proprietary and Confidential Released Issue 4, February 2004 Do wn lo ad ed by Sa nj iv Sh ar m ao fR SB SY ST EM S on RM5231A™ Microprocessor with 32-Bit

GT-64240

Abstract: gt64240 ieee 32 bit floating point multiplier IT8172 RM5261A RM5231A RM7035C RM7065C EV-64120A it8172g
Contextual Info: RM5231A/RM5261A Microprocessors Released 64-Bit MIPS RISC Microprocessors with 32/64-bit System Bus FEATURES Virtually indexed, physically tagged. Write-back and write-through on per-page basis. • Pipeline restart on first double word for data cache misses.

R4000

Abstract: RM5200 RM5231A
Contextual Info: RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary RM5231A RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 3, February 2002 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

block diagram i3 processor

Abstract: implementing ALU with adder/subtractor pin diagram i3 processor R4000 MICROPROCESSOR R4000 RM5200 RM5231A
Contextual Info: RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary RM5231A RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 2, September 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Contextual Info: RM5231 Microprocessor with 32-Bit System Bus Document Rev. 1.3 Date: 01/2000 FEATURES • Dual Issue superscalar microprocessor — 150, 200, & 250 MHz operating frequencies — 300 Dhrystone2.1 MIPS • System interface optimized for embedded applications

Contextual Info: :1 5: 18 PM RM5231A Microprocessor with 32-Bit System Bus Data Sheet Released Th ur sd ay ,2 8O ct ob er ,2 00 4 02 RM5231A Data Sheet Proprietary and Confidential Released Issue 4, February 2004 Do wn lo ad ed by C on te n tT ea m of Pa rtm in er In co

Contextual Info: :4 5: 23 AM RM5231A Microprocessor with 32-Bit System Bus Data Sheet Released es da y, 14 Se pt em be r, 20 04 06 RM5231A Data Sheet Proprietary and Confidential Released Issue 4, February 2004 Do wn lo ad ed by Co nt e nt Te a m of P ar tm in er In co

RM5231

Abstract: MS-022 R4000 RM5200 ALU of 4 bit adder and subtractor by917
Contextual Info: RM5231 Microprocessor with 32-Bit System Bus Data Sheet Released RM5231 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet Proprietary and Confidential Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

MS-022

Abstract: R4000 RM5200 RM5231
Contextual Info: 06 :14 :26 AM RM5231 Microprocessor with 32-Bit System Bus Data Sheet Released on Th ur sd ay ,0 8A ug us t, 20 02 RM5231 Data Sheet Proprietary and Confidential Do wn loa de db yt am er na bil of Si lic on Ex pe rt RM5231™ Microprocessor with 32-Bit

R4000

Abstract: RM5200 RM5231A stream register cache coherency RM5231A-250H
Contextual Info: RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary RM5231A RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

RM5261

Abstract: R4000 R4650 R5000 RM5200 RM5231
Contextual Info: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released RM5261 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Proprietary and Confidential Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

LIC AGENTS DATA

Abstract: RM5261 R4000 R4650 R5000 RM5200 RM5231 RM5261-250Q
Contextual Info: 06 :20 :48 AM RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released on Th ur sd ay ,0 8A ug us t, 20 02 RM5261 Data Sheet Proprietary and Confidential Do wn loa de db yt am er na bil of Si lic on Ex pe rt RM5261™ Microprocessor with 64-Bit

GT-6424

Contextual Info: RM7935/RM7965 Microprocessors Released RM7935/RM7965 64-bit Microprocessors with Integrated L2 Cache and EJTAG FEATURES High-performance Floating Point Unit IEEE 754 . • Fixed-point DSP instructions such as Multiply/Add, Multiply/Subtract, and 3 Operand Multiply.

Contextual Info: :4 0: 49 PM RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released co n Fr id ay ,2 9O ct ob er ,2 00 4 01 RM5261 Data Sheet Proprietary and Confidential Issue 1, March 2001 Do wn lo ad ed by Co nt e nt T ea m of Pa rtm in er In RM5261™ Microprocessor with 64-Bit

Contextual Info: 07 :2 1: 57 P M RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released In co n Tu es da y, 24 Ja nu ar y, 20 12 RM5261 Data Sheet Proprietary and Confidential Issue 1, March 2001 Do wn lo a de d [c on tro lle d] by Co n te nt Te am of Pa rtm in

rm7035c

Abstract: MIPS RM7965 CM5470
Contextual Info: CM5470 Preliminary GEN-M7K-56-000 Data Sheet PM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 1: 59 System Clock Generator For MIPS-Based Designs 00 5 10 :1 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and

RM7035C

Contextual Info: CM5470 Preliminary GEN-M7K-56-000 Data Sheet AM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 2: 24 System Clock Generator For MIPS-Based Designs 04 09 :1 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and

rm7065c

Contextual Info: CM5470 Preliminary GEN-M7K-56-000 Data Sheet AM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 0: 50 System Clock Generator For MIPS-Based Designs 5 02 :2 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and