PRIL1993 Search Results

74AC16543

Abstract: 8C12 IR 3109
Contextual Info: 74AC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS125A —D3475, MARCH 1990-R EVISEDA PRIL1993 • Member of the Texas Instruments Wldebus Family DL PACKAGE TOP VIEW • Packaged in Plastic 300-mil Shrink Small-Outline Package Using 25-mil

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

tl401

Contextual Info: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCAS046 - D2957. DECEMBER 1986 - REVISED APRIL 1993 54ACT11074. . . J PACKAGE 74ACT11074. . . D OR N PACKAGE * Inputs Are TTL-Voltage Compatible

SRQ10

Contextual Info: 74ACT11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER D3644. OCTOBER 1990-R EV ISE D PRIL1993 DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs 1 2 3 4 5 6 7 qf [ 8

PHL 78 303

Contextual Info: 74AC11593 8-BIT BINARY COUNTER WITH 3-STATE I/O INPUT REGISTERS SCAS202 - MARCH 1992 - REVISED APRIL 1993 DW OR NT PACKAGE TOP VIEW * Parallel 3-State I/O: Register Inputs/ Counter Outputs * Counter Has Direct Overriding Load and Clear a * Flow-Through Architecture Optimizes

Contextual Info: 74AC11273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SCAS0132 - D3442, MARCH 1990 - REVISED APRIL 1993 DW OR NT PACKAGE TOP VIEW * Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators • Flow-Through Architecture to Optimize PCB Layout

Contextual Info: 54AC11109,74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _D2957, MARCH 1987 - REVISED APRIL 1993 54AC11109. . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes