PLDLV22V10 Search Results

Contextual Info: ADVANCED IN FO RM A TIO N P L D L V 2 2 V 10-15 Low Voltage, High Performance 10-Macrocell CMOS PLD Low Voltage, High Speed Upgrade to BiCMOS/Bipolar 22V 10 and CMOS Equivalents • Variable P -term s-U p to 16 per Macrocell, Selectable Output Polarity, Separate Output

intel PLD

Contextual Info: in lj. ¡PLDLV22V10-15 LOW VOLTAGE, HIGH PERFORMANCE 10-MACROCELL CMOS PLD Low Voltage High-Speed Upgrade to Bipolar 22V10 and CMOS Equivalente • Supply Voltage Range 3.0V to 3.6V ■ tpo 15 ns, 50 MHz with Feedback, 83.3 MHz with No Feedback ■ Max Ice = 35 mA

Contextual Info: AIEM&NKgll in te i ¡PLDLV22V10-5 LOW VOLTAGE, ELECTRICALLY ERASABLE 10-MACRQCELL CMOS PLD Low Voltage, Low Current, High Speed Upgrade to BiCMOS/Bipolar 22V10 and CMOS Equivalents 10 Macrocells with Programmable I/O Architecture Registered/ Combinatorial

Contextual Info: JUL 1 £ inlel ÌPLDLV22V10 FAST 10-MACROCELL CMOS PLD Low Voltage Hlgträpeed Upgrade to Bipolar 22V10 and CMOS Equivalents • Supply Voltage Range 3.0V to 3.6V ■ tpo 15 ns, 50 MHz with Feedback, 83.3 MHz with No Feedback ■ Max Icc = 35 mA ■ 12 Dedicated Inputs and 10 I/O Pins

intel iPLDLV22V10

Abstract: 29049
Contextual Info: in te l AIOWAMKSB 0[M F (S1M A ¥0®M ÎPLDLV22V10-5 LOW VOLTAGE, ELECTRICALLY ERASABLE 10-MACRQCELL CMOS PLD Low Voltage, Low Current, High Speed Upgrade to BiCMOS/Bipolar 22V10 and CMOS Equivalents 10 Macrocells with Programmable I/O Architecture (Registered/

2142I

Abstract: V-10-15 intel iPLDLV22V10 intel PLD PLD22V10
Contextual Info: in te . PLDLV22V10-15 LOW VOLTAGE, HIGH PERFORMANCE 10-MACROCELL CMOS PLD Low Voltage High-Speed Upgrade to Bipolar 22V10 and CMOS Equivalents • Supply Voltage Range 3.0V to 3.6V ■ tpo 15 ns, 50 MHz with Feedback, 83.3 MHz with No Feedback ■ Max Icc = 35 mA

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Contextual Info: intei AQWANOS DKI F@1^[M^¥0 M ¡PLDLV22V10-5 LOW VOLTAGE, ELECTRICALLY ERASABLE 1Q-MACROCELL CMOS PLD Low Voltage, Low Current, High Speed Upgrade to BiCMOS/Bipolar 22V10 and CMOS Equivalents 10 Macroceils with Programmable I/O Architecture (Registered/