PDU16F Search Results

Contextual Info: PDU16F data 3  delay devices, inc. 6-BIT PROGRAMMABLE DELAY LINE SERIES PDU16F FEATURES • • • • • • • • PACKAGES Digitally programmable in 64 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting

PDU16F

Abstract: PDU16F-1 PDU16F-2 PDU16F-3 PDU16F-4 PDU16F-5 PDU16F-6 PDU16F-8
Contextual Info: PDU16F data 3  delay devices, inc. 6-BIT PROGRAMMABLE DELAY LINE SERIES PDU16F FEATURES • • • • • • • • PACKAGES Digitally programmable in 64 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting

312F

Contextual Info: Timing Definition For Programmable Delay Lines PDU’s Typical Set-Up Specifications Minimum Input Pulse-Width (ns) Minimum Input Period (ns) T sua (ns) ^SUE (ns) Too (ns) ‘Absolute •Suggested Recommended PDU-13F PDU-14F PDU-15F PDU-16F PDU-17F PDU-18F

16f8

Contextual Info: data detayW devices;inc. 7a s t L o g ic Programmable Delay Units SERIES: PDU-16F 6-Bit TTL Interfaced Features: T es t C o nditions: • Input & Output TTL buffered ■ 6-Bit TTL program m able delay line ■ Two (2) Separate outputs; inverting and non-inverting.

Mdu 1517

Abstract: IC 8783 N
Contextual Info: data delay devieesYinc. Table of Contents Page C o m p a n y P r o f i l e .In s id e F ro n t C o v e r D C E le c tric a l C h a r a c t e r is t ic s . P ro d u c t S e l e c t i o n . 1

Contextual Info: data delay W devices^inc. rasf Logic Programmable Delay Units SERIES: PDU-16F 6-Bit T T L Interfaced Features: T e s t C o n d itio n s : • Input & Output TTL buffered ■ 6-Bit TTL program m able delay line ■ Two (2) Separate outputs; inverting and non-inverting.

Contextual Info: Timing Definition For Programmable Delay Lines PDU’s Typical Set-Up Specifications f DO (ns) M inim um Input Pulso-W idth (ns) ‘ A bsolute •Suggested R ecom m ended M inim um Input Period (ns) 6 5.5 10% of T dt 2 X PW IN 9 9 8% of T dt 8% o l T dt

Contextual Info: Ta s t L o g ic Programmable Delay Units S ER IES : PDU-16F 6-Bit T T L Interfaced Features: Test Conditions: • Input & Output TTL buffered ■ 6-B it TTL program m able delay line ■ Two (2) Separate outputs; inverting and non-inverting. ■ Com pletely interfaced

PDU-1316 Series Programmable Delay Units

Contextual Info: ìFast Logic Multiple Digital SERIES: MDU-38F Delay Units 8 pins DIP T T L Interfaced Features: • Auto-insertable. ■ Completely interfaced for TTL & DTL application. ■ P.C. board space economy achieved. ■ Fits standard 8 pins DIP socket. ■ 3 equal delay units/package.

Contextual Info: MILITARY PRODUCTS Most of Data Delay Devices digital delay line products are available in military version. They are identified as follows: PWC-30 Example: M C3 Series Pulse Width Military Unit_ Case Dimensions The Military Delay Line Products Feature The Following:

Contextual Info: data delay devices^inc. Ta s t Logic Programmable Delay Units SERIES: PDU-16F 6-Bit TTL Interfaced F e a tu re s : Test Conditions: • In p u t & O u tp u t T T L b u ffe re d ■ 6 -B it T T L p r o g ra m m a b le d e la y lin e ■ T w o (2) S e p a ra te o u tp u ts ;

Contextual Info: MILITARY PRODUCTS Most of Data Delay Devices digital delay line products are available in military version. They are identified as follows: Example: PWC-30 35 M C3 Series Pulse Width. Military Unit_ Case Dimensions The Military Delay Line Products Feature The Following:

DU3C

Abstract: smd 312F TTL Logic Family list
Contextual Info: Table of Contents Page Company P r o file .Inside Front Cover Product List By F u n c tio n .2,3

Contextual Info: Test Set-Up And Wave Forms Passive Delay Line Active Delay Une H -CMOS ( c o n tin u e d n e x t p ag e ) 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 • (973) 773-2299 ■ Fax (973) 773-9672 4 Active Delay Line (TTL) W A V E FO R M Active Delay Line (ECL)

ns630

Abstract: 6F-10 PDU-16F-1 PDU-16F-2 PDU-16F-5 PDU-16F-8
Contextual Info: data delay devices; inc. i a s f L o g ic Programmable Delay Units S ER IES : PDU-16F 6-Bit T T L Interfaced F e a tu re s : Test Conditions: • In p u t & O u tp u t T T L b u ffe re d ■ 6 - B it T T L p r o g ra m m a b le d e la y lin e ■ T w o (2 ) S e p a ra te o u tp u ts ;

PDU-13256 Series Programmable Delay Units

Abstract: DDU-4 Series Digital Delay Units DDU-11 Series Programmable Delay Units
Contextual Info: data \ delay ^O/ deVlcesYin»: THE SOllRtE Programmable Passive data W delay \ü / devieesYinc. GENERAL INFO RM ATIO N ORDER INFORMATION: COMPANY PROFILE DATA DELAY DEVICES, INC. was founded in 1964 with the goal of becom ing a major supplier of delay line

Contextual Info: data delay devices^inc. ïFast Logic Programmable Delay Units S ER IES : PDU-16F 6-Bit T T L Interfaced Features: Test Conditions: • Input & Output TTL buffered ■ 6-Bit TTL program m able delay line ■ Two (2) Separate outputs; inverting and non-inverting.

PDU-16F-1

Abstract: PDU-16F-10 PDU-16F-2 PDU-16F-3 PDU-16F-4 PDU-16F-5 PDU-16F-6 PDU-16F-8
Contextual Info: • I L O g iC Programmable Delay Units SERIES: PDU-1 6 F 6-Bit T T L Interfaced Features: data \</3W delay W devicesYinc. T e s t C o nditions: ■ Input & Output TTL buffered ■ 6-B it TTL program m able delay line ■ Two (2) Separate outputs; inverting and non-inverting.

Contextual Info: 7ast Logic d a ta V ^ V d e la y W devicesVinc. Programmable Delay Units SERIES: PDU-16F 6-Bit T T L Interfaced Features: T es t C onditions: • Input & Output TTL buffered ■ 6-B it TTL program m able delay line ■ Two (2) Separate outputs; inverting and non-inverting.

Contextual Info: i a s f L o g ic data delay devices^me. Programmable Delay Units PDU-16F S ER IES ; 6-Bit T T L Interfaced Features: T e s t C o nditions: • Input & Output TTL buffered ■ 6-Bit TTL programmable delay line ■ Two (2) Separate outputs; inverting and non-inverting.

Mdu 1517

Abstract: 1519 Series smd 312F
Contextual Info: dataYgy delay No / devicesYinc. Table of Contents Page Company P ro file .Inside Front Cover Product Selection. 1 List By F unctio