PDM41252 Search Results

PD-23

Contextual Info: P A R A D I G M T E C H N O L O G Y INC ETE D • LTMICHQ OOOOQHS 1 ■ 256K Static RAM 64K x 4-Bit with Separate I/O T ‘ % ' 2 3 ' /O PDM41251S/L PDM41252S/L Features Description □ Separate data input and output pins □ High speed access times Com'l: 1 5 ,2 0 ,2 5 ,3 5 and 45ns

data book transistors 2SA

Abstract: PDM41251LA
Contextual Info: PDM41251 PDM41252 256K Static RAM 64K x 4-Bit with Separate I/O Features Description • High speed access times Com’l: 7, 8, 10, 12 and 15 ns Ind’l: 8, 10, 12, and 15 ns The PDM41251 and PDM41252 are highperformance CMOS static RAMs organized as 65,536 x 4 bits. This product is produced in

Contextual Info: PARADIGM 256K Static RAM 64K x 4-Bit with Separate I/O PDM41251SA/LA PDM41252SA/LA Features Description □ High speed access times Com'l: 1 0 ,1 2 ,1 5 ,2 0 and 25ns M il: 12,15, 20,25, 35,45, and 55ns □ Separate data input and output pins □ Low power operation

Contextual Info: PARADIGM TECHNOLOGY PARADEM I INC SDE D bTMlGTO 000G115 S «PAT "P H frtV lO 256K Static RAM 64K x 4-Bit with Separate I/O PDM41251SA/LA PDM41252SA/LA Features Description □ High speed access times Com'l: 1 0 ,1 2 ,1 5 ,2 0 and 25ns M il: 1 2 ,1 5 ,2 0 ,2 5 ,3 5 ,4 5 , and

Contextual Info: PARADIGM 256K Static RAM 64K x 4-Bit w ith Separate I/O PDM41251SA/LA PDM41252SA/LA Features Description □ High speed access times Com'l: 1 0 ,1 2 ,1 5 ,2 0 and 25ns M il: 1 2 ,1 5 , 20, 25, 35, 45, and 55 ns □ Separate data input and output pins □ Low pow er operation

Contextual Info: Paradigm 256K Static RAM 64K x 4-Bit with Separate I/O PDM41251SA/LA PDM41252SA/LA Features Description □ High speed access times Com'l: 10,12,15,20 and 25ns M il: 12,15,20,25,35,45, and 55ns □ Separate data input and output pins □ Low power operation

Contextual Info: MAR ? '991 PARADIGM' 256K Static RAM 64K x 4-Bit with Separate I/O PDM41251S/L PDM41252S/L Features Description □ Separate data input and output pins □ High speed access times Com'l: 1 5 ,2 0 ,2 5 ,3 5 and 45ns M il: 20, 25, 35, 45, and 55ns □ Low power operation

Contextual Info: PDM41251 SA/LA PDM41252SA/LA PARADIGM 256K Static RAM 64K x 4-Bit with Separate I/O Features Description n High speed access times Com'l: 8 ,1 0 ,1 2 ,1 5 , 20 and 25 ns Ind'l: 10,12,15, 20, and 25 ns The PDM41251 and PDM41252 are highperformance CMOS static RAMs organized as

Contextual Info: PARAEÎGM' PDM41251 SA/LA PDM41252SA/LA bW CH G Q Q Q Q 3SC1 «Ï5Û 256K Static RAM 64K x 4-Bit with Separate I/O IP AT Features Description □ High speed access times Com'l: 1 0 ,1 2 ,1 5 ,2 0 and 25ns M il: 12,15, 20,25, and 35ns The PDM41251 and PDM41252 are high

Contextual Info: Paradigm 256K Static RAM 64K x 4-Bit with Separate I/O PDM41251SA/LA PDM41252SA/LA Features Description □ High speed access times Com’l: 1 0 ,1 2 ,1 5 ,2 0 and 25ns M il: 1 2 ,1 5 ,2 0 ,2 5 ,3 5 ,4 5 , and 55ns □ Separate data input and output pins □ Low power operation

Contextual Info: PARADIGM Product Family MODULES Secondary Level Cache Modules Static RAM Modules • • • • • • • • PDM4M096S PDM4M096L PDM4M4030 PDM4M4040 PDM4M4050 PDM4M4060 PDM4M4110 PDM4M4120 512K x 8 Asynchronous (512K x 8 Asynchronous) (64Kx 32 Asynchronous)

CY7B192-12

Abstract: CY7B192-15 IDT71282L-25 IDT71282L-35
Contextual Info: 117 — — 2 5 6 K m « £ iä m m CO X TAAC TCAC TOE •ax max ■ax ns (ns) (ns) CMOS S t a t i c RAM ( 6 5 5 3 6 X 4 ) A v + V '/ ft « TOH TOD ■in max (ns) (ns) TWP TDS ■in ■in (ns) (ns) TDH TWD T ’ VR min min (ns) (ns) ■ax (ns) V D D or V C C