NT5CB256M8GN
Abstract: NT5CC256M8GN NT5CB256M8GN-DI NT5CC256M8GN-D NT5CC512M4GN NT5CC512M4GN-CG NT5CB256M8GN-CG "2Gb DDR3 SDRAM" NT5C NT5CB256M8
Contextual Info: 2Gb DDR3 SDRAM G-Die NT5CB512M4GN / NT5CB256M8GN NT5CC512M4GN / NT5CC256M8GN Feature VDD = VDDQ = 1.5V ± 0.075V JEDEC Standard Programmable Burst Length: 4, 8 Power Supply 8n-bit prefetch architecture VDD = VDDQ = 1.35V -0.0675V/+0.1V Output Driver Impedance Control
|
Original
|
nt5cb512m4gnnt5cb256m8gnnt5cc512m4gnnt5cc256m8gn+878ballsnt5cb256m8gn-dint5cc256m8gn-dnt5cc512m4gn-cgnt5cb256m8gn-cg2gb ddr3 sdramnt5cnt5cb256m8
|
PDF
|
NT5CC256
Abstract: NT5CB256M8GN- CG
Contextual Info: 2Gb DDR3 SDRAM G-Die NT5CB512M4GN / NT5CB256M8GN NT5CC512M4GN / NT5CC256M8GN Feature 1.35V -0.0675V/+0.1V & 1.5V ± 0.075V JEDEC Output Driver Impedance Control Standard Power Supply Differential bidirectional data strobe 8 Internal memory banks (BA0- BA2)
|
Original
|
nt5cb512m4gnnt5cb256m8gnnt5cc512m4gnnt5cc256m8gn+378ballsnt5cc256nt5cb256m8gn- cg
|
PDF
|
DDR3-1866-CL12
Abstract: NT5CB256M8GN-DI
Contextual Info: 2Gb DDR3 SDRAM G-Die NT5CB256M8GN / NT5CC256M8GN Feature Table 1: CAS Latency Frequency Speed Bins -BE* -CG/CGI* -DI* -EJ* DDR3 L -1066-CL7 DDR3 (L)-1333-CL9 DDR3(L)-1600-CL11 Units DDR3-1866-CL12 Parameter Min. Max. Min. Max. Min. Max. Min. Max. tCK(Avg.)
|
Original
|
nt5cb256m8gnnt5cc256m8gn-1066-cl7-1333-cl9+3-1600-cl11ddr3-1866-cl12nt5cb256m8gn-di
|
PDF
|
NT5CC256
Contextual Info: 2Gb DDR3 SDRAM G-Die NT5CB512M4GN / NT5CB256M8GN NT5CC512M4GN / NT5CC256M8GN Feature 1.35V -0.0675V/+0.1V & 1.5V ± 0.075V JEDEC Output Driver Impedance Control Standard Power Supply Differential bidirectional data strobe 8 Internal memory banks (BA0- BA2)
|
Original
|
nt5cb512m4gnnt5cb256m8gnnt5cc512m4gnnt5cc256m8gn+278ballsnt5cc256
|
PDF
|
NT5CB256M8GN-CG
Abstract: NT5CB256M8GN NT5CC512M4GN-CG NT5CC256M8GN-D NT5CB256M8GN- CG NT5CC256M8GN-DI
Contextual Info: 2Gb DDR3 SDRAM G-Die NT5CB512M4GN / NT5CB256M8GN NT5CC512M4GN / NT5CC256M8GN Feature VDD = VDDQ = 1.5V ± 0.075V JEDEC Standard Programmable Burst Length: 4, 8 Power Supply 8n-bit prefetch architecture VDD = VDDQ = 1.35V -0.0675V/+0.1V Output Driver Impedance Control
|
Original
|
nt5cb512m4gnnt5cb256m8gnnt5cc512m4gnnt5cc256m8gn+678ballsnt5cb256m8gn-cgnt5cc512m4gn-cgnt5cc256m8gn-dnt5cb256m8gn- cgnt5cc256m8gn-di
|
PDF
|