MC100E1 Search Results

E212 transistor

Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Contextual Info: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

marking CODE D2B

Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

MC100E116

Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
Contextual Info: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.

MC100E171

Abstract: MC10E171 MC10E171FN
Contextual Info: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

MC100E151

Abstract: MC10E151 MC10E151FN
Contextual Info: MC10E151, MC100E151 5V ECL 6-Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous

MC100E150

Abstract: MC10E150 MC10E150FN
Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

E112

Abstract: E212 MC100E112 MC10E112 E212 transistor
Contextual Info: MC10E112, MC100E112 5V ECL Quad Driver Description The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

MC100E163

Abstract: MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2
Contextual Info: MC10E163, MC100E163 5VĄECL 2ĆBit 8:1 Multiplexer The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 – A7, B0 – B7) is propagated to the output.

MC100E154

Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
Contextual Info: MC10E154, MC100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on

MC100E157

Abstract: MC100E157FN MC100E157FNR2 MC10E157 MC10E157FN MC10E157FNR2
Contextual Info: MC10E157, MC100E157 5VĄECL Quad 2:1 Multiplexer The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select control makes the devices well suited for random logic designs.

pdc 140

Abstract: DL140 E195 MC100E195 MC10E195
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 MC100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.

motorola D-latch

Abstract: MC100E150 DL140 MC10E150
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6ĆBit D Latch MC10E150 MC100E150 The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A

DL140

Abstract: E195 MC100E195 MC10E195
Contextual Info: MOTOROLA Order this document by MC10E195/D SEMICONDUCTOR TECHNICAL DATA MC10E195 MC100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.

Motorola, Inc. identical in pinout to

Abstract: DL140 MC100E171 MC10E171
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit 4:1 Multiplexer MC10E171 MC100E171 The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control which one of the

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E175 MC100E175 9-bit Latch Parity Detection/Generation 800 ps Max. D to Output Reset Extended 100E VEE Range of -4.2V to -5.46V Internal 7 5 k fi Input Pulldown Resistors The MC 10E/1OOE175 is a 9-bit latch. It also features a tenth latched output,

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 5-Bit 2:1 M ultiplexer The M C 10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input SEL . M C10E158 MC100E158 • 600ps Max. D to Output • 800ps Max. SEL to Output

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA • • • • MC10E104 MC100E104 600 ps Max. Propagation Delay OR/NOR Function O utputs Extended 100E Vgg Range o f - 4 .2 V to -5 .4 6 V 75 k il Input Pulldow n Resistors The MC10E/100E104 is a q u in t 2-input AN D/NAND gate. The fu n ctio n o u tp u t F is

MC100E111

Abstract: MC100E111FN MC100E111FNR2 MC10E111 MC10E111FN MC10E111FNR2
Contextual Info: MC10E111, MC100E111 5V ECL 1:9 Differential Clock Driver The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output

MC100E101

Abstract: MC10E101 MC10E101FN MC10E101FNG
Contextual Info: MC10E101, MC100E101 5V ECL Quad 4-Input OR/NOR Gate Description The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. http://onsemi.com Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: •

MC100E166

Abstract: MC10E166 MC10E166FN
Contextual Info: MC10E166, MC100E166 5V ECL 9-Bit Magnitude Comparator Description The MC10E/100E166 is a 9-bit magnitude comparator which compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other. The 100 Series contains temperature compensation.

MC100E155

Abstract: MC10E155 MC10E155FN
Contextual Info: MC10E155, MC100E155 5V ECL 6−Bit 2:1 Mux−Latch Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic

MC100E156

Abstract: MC10E156 MC10E156FN
Contextual Info: MC10E156, MC100E156 5V ECL 3-Bit 4:1 Mux-Latch Description The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output date is

MC10E160FN

Abstract: MC10E160FNR2 MC100E160 MC100E160FN MC100E160FNR2 MC10E160
Contextual Info: MC10E160, MC100E160 5V ECL 12-Bit Parity Generator/Checker The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input EN forces the Q output LOW. The 100 Series contains temperature compensation.

Contextual Info: MC100LVE111 3.3V ECL 1:9 Differential Clock Driver The MC100LVE111 is a low skew 1−to−9 differential driver, designed with clock distribution in mind. The MC100LVE111’s function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input,