LVCH32374A Search Results

Contextual Info: 3.3V CMOS 32-BIT LVCH32374A EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, INFORMATION 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH32374A 32-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. This high­

Contextual Info: LVCH32374A 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE LVCH32374A 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION: FEATURES: The LVCH32374A 32-bit edge-triggered D-type flip-flop is built using

Contextual Info: LVCH32374A 3.3V CMOS 32-BIT ADVANCE EDGE TRIGGERED D-TYPE INFORMATION FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: The LVCH32374A 32-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. This high­

Contextual Info: 3.3V CMOS 32-BIT LVCH32374A EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, INF0RMATI0N 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH32374A 32-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. This high­

Contextual Info: 3.3V CMOS 32-BIT LVCH32374A EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, INF0RMATI0N 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH32374A 32-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. This high­

Contextual Info: 3.3V CMOS 32-BIT LVCH32374A EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, INFORMATION 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH32374A 32-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. This high­

IDT74LVCH32374A

Abstract: LVCH32374A
Contextual Info: LVCH32374A 3.3V CMOS 32-BIT ADVANCE EDGE TRIGGERED D-TYPE INFORMATION FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD Integrated Device Technology, Inc. FEATURES: DESCRIPTION: – Typical tSK o (Output Skew) < 250ps – ESD > 2000V per MIL-STD-883, Method 3015;

IDT74LVCH32374A

Abstract: LVCH32374A
Contextual Info: LVCH32374A 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE LVCH32374A 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION: FEATURES: – – – –

marking code A45

Abstract: marking code B38 RC3740 TSSOP YAMAICHI SOCKET SCEA014 MARKING a47 marking b28 RC3041 RC3715 RC4650
Contextual Info: 32-Bit Logic Families in LFBGA Packages: 96 and 114 Ball Low-Profile Fine-Pitch BGA Packages SCEA014 October 1998 1 2  32-Bit Logic Families in LFBGA Packages: 96 and 114 Ball Low-Profile Fine-Pitch BGA Packages Application Note October 26th, 1998 by: Sylvie Kadivar, Philips Semiconductors

RC3041

Abstract: RC3715 RC3740 RC4650 IDT package marking LVCH OREGA
Contextual Info: 32-Bit Logic Families in LFBGA Packages: 96 and 114 Ball Low-Profile Fine-Pitch BGA Packages Application Note October 26th, 1998 by: Sylvie Kadivar, Philips Semiconductors Maria Balian, Texas Instruments Ed Agis, Texas Instruments Valentino Liva, Integrated Device Technology

TSSOP YAMAICHI SOCKET

Abstract: TSSOP-56 footprint texas JEDEC Jc-11 mo-205 free IDT marking IDT package marking LVCH JEDEC Jc-11 free OREGA IC280-096-144 marking B44 RC3041
Contextual Info: 32 Bit Logic Families in LFBGA packages: 96 and 114 Balls Low Profile Fine Pitch BGA Packages. Application Note. October 26th, 1998 by: Sylvie Kadivar, Philips Semiconductors Maria Balian, Texas Instruments Ed Agis, Texas Instruments Valentino Liva, Integrated Device Technology