LVC533A Search Results

Contextual Info: 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O LVC533A ADVANCE INFORMATION D E S C R IP TIO N : FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; The LVC533A octal transparent D-type latch is built using advanced dual

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

LVC533A

Contextual Info: LVC533A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: – – – – – – – – – – LVC533A ADVANCE

Contextual Info: 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP,

Contextual Info: 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1.27mm pitch SOIC, 0.65mm pitch SSOP,