LVC16823A Search Results

Contextual Info: 3.3 V CMOS 18-BIT REGISTER 3-STATE , 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - LVC16823A ADVANCE INFORMATION The LVC16823A18-bit edge-triggered D-type register is built using advanced dual metal CMOS technology.This high-speed, low-power register is ideal for use as a buffer register for data

Contextual Info: LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: The LVC16823A 18-bit register is built using advanced dual metal CMOS

Contextual Info: 3.3 V CMOS 18-BIT REGISTER 3-STATE , 5 VOLT TOLERANT I/O jd t LVC16823A ADVANCE INFORMATION Integrated D ev ice Ife ch n o ljg y , l i e . DESCRIPTION: FEATURES: - The LVC16823A18-bit edge-triggered D-type register is built using advanced dual metal CMOS technology. This high-speed,

IDT74LVC16823A

Abstract: LVC16823A SO56-2
Contextual Info: LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: – – – – – – – – – DESCRIPTION: Typical tSK 0 (Output Skew) < 250ps

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

Contextual Info: LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

Contextual Info: 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O BE FEATURES: - Typical tsK o (Output Skew) < 250ps - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages

Contextual Info: LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

DSC-4573

Abstract: IDT74LVC16823A LVC16823A
Contextual Info: LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

Contextual Info: ID T74L VC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: - D E S C R IP TIO N : Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP

IDT74LVC16823A

Abstract: LVC16823A
Contextual Info: LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

Contextual Info: FEATU RES: DESCRIPTION: - Typical tsK o (Output Skew) < 250ps - - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages Extended commercial range of -40°C to +85°C